• artificial intelligence
• CloudScout
• convolutional neural network
• Esa
• fpga
• hardware acceleration
• partial reconfigurability
• space application

The thesis proposes a method to design and implement an FPGA-based hardware accelerator for convolutional neural network exploiting partial reconfiguration (PR), a modern FPGA functionality allowing to reconfigure a partition of the FPGA while the remaining part continues to operate without interruptions. The chosen case study is the CloudScout CNN, a network developed in the frame of the phi-sat-1 ESA mission and consisting in the first implementation of an AI algorithm aboard a satellite for cloud-detection. Starting from an existing FPGA implementation of the CloudScout CNN, a new PR-based design is proposed to decrease the resource utilization of the previous implementation and improve the network portability on smaller FPGA. The proposed design was then implemented on FPGA, validated, characterized and compared with the previous one. The results show the efficacy of the approach, confirming the reduction in resource utilization and the consequent improvement in network portability.