• environment
• ESA
• eVC
• functional
• funzionale
• HDL
• HVL
• IEEE
• NASA
• reuse
• spacewire
• SpaceWire
• Specman
• verifica
• verification
• VLSI

In digital circuit design flows, functional verification is the task of verifying that the logic design conforms to specification. This is a complex task, and takes the majority of time and effort in most large electronic system design projects (about 60-70% of the project's cost).
Time-to-market must be met not only by hardware designers, but also by the verification engineers. Since isolated testbench tools have certain limitations, to produce a significant boost in productivity a complete verification automation system that offers a comprehensive environment for all aspects of functional verification is needed.
This thesis focuses on the design and implementation of a SpaceWire interface verification environment by means of the Cadence Specman tools and the e language, an Hardware Verification Language (HVL) used for functional verification of digital systems and integrated circuit designs, that represents the current state-of-the-art language for verifying hardware components at various abstraction levels. The so produced verification environment is also called eVC (e Verification Component).
SpaceWire is a standard for high-speed links and networks, based on the IEEE 1355 standard of communications: it is a low cost, low latency, scalable serial interconnection system, originally intended for communication between large numbers of inexpensive computers. SpaceWire is coordinated by the European Space Agency (ESA) in collaboration with several European space companies.