ETD system

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Tesi etd-05312010-111419


Thesis type
Tesi di laurea specialistica
Author
FALASCHI, FRANCESCO
URN
etd-05312010-111419
Title
Design and verification of the FPGA-based digital front-end for the SLSTR instrument
Struttura
INGEGNERIA
Corso di studi
INGEGNERIA ELETTRONICA
Commissione
relatore Ing. Rovini, Massimo
relatore Prof. Fanucci, Luca
Parole chiave
  • Altera
  • verifica
  • verification
  • progettazione
  • VHDL
  • design
  • FPGA
  • front-end
  • digitale
  • digital
  • Actel
  • SLSTR
Data inizio appello
25/06/2010;
Consultabilità
parziale
Data di rilascio
25/06/2050
Riassunto analitico
This thesis describes the architecture design, system verification and implementation phases on different FPGA technologies of a digital front-end electronics. The circuit is used to drive the analog channels of some optical detectors in order to acquire science data and transmit them using the SpaceWire standard for serial high-speed communications and networking. It will have to operate in a high-radiation environment, therefore its physical implementation requires the employment of radiation-tolerant technologies.
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