• ahb
• amba
• coverage
• evc
• functional verification
• network-on-chip
• noc
• soc
• specman

Designers of complex digital systems (ASIC, application-specific/general-purpose microprocessors (MP), etc.) need verification methods and tools to guarantee a perfect design before the process of its manufacturing is started. Verification presents about 60-70% of the total design effort and only advances in verification methodology can improve the time to market considerably.
Directed tests and 'golden' reference files will soon become the primitive tools of the modern test environment. Verification engineers are consequently looking towards new methodologies like Constrained-Random, Coverage-Driven and Reuse approach to reduce testbench development time, and speed-up the time it takes to achieve complete verification of their ASIC or SoC. Testbench automation tools for constrained-random stimulus generation and functional coverage create tests for corner cases that even engineers who designed the system may not anticipate and hence find bugs early in the development cycle.
There exist several commercial offerings addressing the area of SoC functional verification.
In this context we will show Specman Elite and its language e of Cadence Inc, and we compare it to SystemVerilog that represent today one of the most used tool for functional verification. This thesis is structured to provide information on the state of the art in the area of functional verification and we will focus on existing methodologies, tools, and practical approaches based on the development of a verification component for testing some Networks-on-Chip features of a STNoC Network Interface (AST Microelectronics Grenoble approach to NoCs) using Specman.
We also present another approach to build a verification environment by using an e Verification Component, just development from Cadence using the eRM, ready to use and configurable to work in any environment in a plug and play manner.