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Digital archive of theses discussed at the University of Pisa


Thesis etd-05082021-111449

Thesis type
Tesi di dottorato di ricerca
Thesis title
Design of Delta-Sigma Modulators for Ultra-Low-Voltage Scenarios
Academic discipline
Course of study
tutor Prof. Bruschi, Paolo
correlatore Prof. Fanucci, Luca
supervisore Ing. Serventi, Riccardo
  • delta-sigma modulator
  • energy harvesting
  • inverter-like
  • ultra-low-power
  • ultra-low-voltage
Graduation session start date
The demand for low-power, low-voltage circuits in both battery-powered and battery-less systems for Internet of Things rose significantly in the last years, thanks to significant applications such as biomedical implantable devices, wearables and many others. Analog to Digital Converters (ADCs) are fundamental building
blocks in every data acquisition system, being necessary to translate the analog information coming from a sensor to the digital world. Among ADCs, Delta-Sigma modulators are one of the best choices when the required resolution starts to increase, because they are not as sensitive to circuit non-idealities as other architectures are. In this context, we developed three Delta-Sigma modulators: a simpler, single-ended, 1st order architecture and two more complex, 2nd order ones, in both single-ended and fully-differential versions.
All three of them are inverter-based systems: inverter-like amplifiers are particularly suitable in ultra-low voltage design thanks to their rail-to-rail output range and their excellent trade-off between speed, noise, and power performances. The modulators also exploit an original switched-capacitor integrator to overcome some of the operatingscenario intrinsic limitations, such as the low DC gain of the amplifiers. Furthermore, a
clock-boosting technique was adopted to improve the performances of the switches, reducing their on-resistance. The designs were realized using the UMC 0.18 um CMOS process. The 1st order modulator is a single-ended architecture, it was realized on a test-chip and measurements were performed to assess its performances. It reaches an SNDR of 37.2 dB at a voltage down to of 0.25 V, with a power consumption of only 2.1 nW and a bandwidth of 42.9 Hz, corresponding to a Schreier Figure of Merit (FoMS) of 140.3 dB. The 2nd order modulators are a little less simple. In particular, the fully-differential architecture requires a mechanism to stabilize the Common-Mode (CM): this was achieved by a novel CM stabilization loop implemented in an amplifier that outperforms the Nauta transconductor under many aspects. The modulator was validated by means of electrical simulations performed using Cadence VirtuosoTM: at a supply voltage of 0.3 V, it reaches an SNDR of 73.1 dB, with a bandwidth of 640 Hz and a power consumption of 200.5 nW, corresponding to a FoMS of 168.1 dB. Furthermore, Monte Carlo sampling and temperature simulations were performed to evaluate its robustness in regard to PVT variations. Waiting for its validation on a silicon test chip, it represent an evident improvement with respect to the 1st order modulator. It is also possible to make our Delta-Sigma converters work with higher voltages, increasing in this way the bandwidth and, of course, the power consumption. This versatility makes them very useful for the digital conversion of low frequency and DC signals, as in the case
of energy scavenging systems.