• Intelligent Power Switch
• Integrated Circuits
• High Voltage CMOS
• High Energy Physics experiments readout
• automotive electronics
• architectures and circuits for harsh environments
• radiation tolerance
• serial communications

In this thesis an overview of the research activity focused on development, design
and testing of electronic devices and systems for harsh environments has been
reported. The scope of the work has been the design and validation flow of
Integrated Circuits operating in two harsh applications: Automotive and High
Energy Physics experiments.
In order to fulfill the severe operating electrical and environmental conditions of
automotive applications, a systematic methodology has been followed in the
design of an innovative Intelligent Power Switch: several design solutions have
been developed at architectural and circuital level, integrating on-chip selfdiagnostic
capabilities and full protection against high voltage and reverse polarity,
effects of wiring parasitics, over-current and over-temperature phenomena.
Moreover current slope and soft start integrated techniques has ensured low EMI,
making the Intelligent Power Switch also configurable to drive different interchangeable
loads efficiently. The innovative device proposed has been
implemented in a 0.35 μm HV-CMOS technology and embedded in mechatronic
3rd generation brush-holder regulator System-on-Chip for an automotive alternator.
Electrical simulations and experimental characterization and testing at componentlevel
and on-board system-level has proven that the proposed design allows for a
compact and smart power switch realization, facing the harshest automotive
conditions. The smart driver has been able to supply up to 1.5 A to various types of
loads (e.g.: incadescent lamp bulbs, LED), in operating temperatures in the wide
range -40 °C to 150 °C, with robustness against high voltage up to 55 V and
reverse polarity up to -15 V.
The second branch of research activity has been framed within the High Energy
Physics area, leading to the development of a general purpose and flexible
protocol for the data acquisition and the distribution of Timing, Trigger and Control
signals and its implementation in radiation tolerant interfaces in CMOS 130 nm
technology. The several features integrated in the protocol has made it suitable for
different High Energy Physics experiments: flexibility w.r.t. bandwidth and latency
requirements, robustness of critical information against radiation-induced errors,
compatibility with different data types, flexibility w.r.t the architecture of the control
and readout systems, are the key features of this novel protocol.
Innovative radiation hardening techniques have been studied and implemented in
the test-chip to ensure the proper functioning in operating environments with a high
level of radiation, such as the Large Hadron Collider at CERN in Geneva.
An FPGA-based emulator has been developed and, in a first phase, employed for
functional validation of the protocol. In a second step, the emulator has been
modified as test-bed to assess the Transmitter and Receiver interfaces embedded
on the test-chip. An extensive phase of tests has proven the functioning of the
interfaces at the three speed options, 4xF, 8xF and 16xF (F = reference clock
frequency) in different configurations.
Finally, irradiation tests has been performed at CERN X-rays irradiation facility,
bearing out the proper behaviour of the interfaces up to 40 Mrad(SiO2).