• wire delay
• nuca
• leakage
• cmp

Large last level caches are a common design choice for today’s high performance microprocessors, but ever shrinking feature size and high clock frequencies exacerbate the wire delay problem: wires don’t scale as transistors do, and their latency is going to be the main component of cache access time. Further, leakage power is becoming the main power issue for large LLC caches in deep sub-micron processes.
NUCA (Non Uniform Cache Architecture) caches limit the impact of wire delays on performances by aggressively partitioning the cache into independently accessible small and fast sub-banks, interconnected by a scalable network-on-chip. D-NUCA caches, in particular, implement a migration mechanism on frequently accessed data by dynamically moving them into the banks closer to the controller, hence accessed faster.
By leveraging their modularity and the non uniform distribution of data it is possible to apply to D-NUCA caches a microarchitectural leakage reduction technique, the Way-Adaptable D-NUCA, which applies power gating to groups of underutilized banks, dynamically resizing the cache in the course of the application.
This thesis evaluates the effectiveness of this technique in a multiprocessor environment and explores different optimizations to enhance its efficiency; in particular, alternative resizing algorithms are investigated.
The Way Adaptable technique is then compared to other leakage reduction techniques proposed in literature, Decay Lines Cache and Drowsy Cache, in order
to determine the additional leakage savings when circuital fine grained leakage reduction schemes at line level are applied to D-NUCA caches.
Finally, a leakage reduction scheme combining Way Adaptable and Drowsy Cache, in order to cope with leakage reduction limits posed by statistical process variation effects of nanometer processes, is proposed and evaluated.