ETD system

Electronic theses and dissertations repository

 

Tesi etd-04252016-231359


Thesis type
Tesi di dottorato di ricerca
Author
CASSETTARI, RICCARDO
URN
etd-04252016-231359
Title
Embedded digital signal processing for on-board satellite and vehicle systems
Settore scientifico disciplinare
ING-INF/01
Corso di studi
INGEGNERIA
Supervisors
tutor Prof. Fanucci, Luca
Parole chiave
  • space
  • Digital signal processing
  • automotive
Data inizio appello
25/05/2016;
Consultabilità
Parziale
Data di rilascio
25/05/2019
Riassunto analitico
The research activity reported in this thesis is focused on the study of efficient solutions
to meet the challenges in the design of electronic systems for satellites and vehicles,
and more particularly on blocks of digital signal processing within these systems. More
in detail, this thesis describes three research activities on innovative solutions for some
sub-systems related to the fields of space and vehicles.
The first research activity is devoted to the realization of a transponder Telemetry,
Tracking & Command (TT&C) innovative optimized for small satellites with type Earth
Observation missions (EO). The activity was carried out in collaboration with Intecs and
Sitael companies. The miniaturization of the satellite is a more and more important factor,
as it allows to reduce the mission costs due to the reduction of the satellite’s mass. One
of the most innovative aspects of the system is therefore the integration of the scientific
data transmission unit with the TT&C sub-system of the satellite in a single FPGA device,
which allows to reduce the mass of the electronics board. Another innovative aspect of
the system developed is the in-flight re-configurability of the communication parameters in
order to optimize the communication link between the Earth and the satellite. This feature
is very important for satellites for Earth Observation, which typically have a Low Earth
Orbit (LEO). The designed system includes a part of signal processing in the transmission
and reception chains and a control part and interface with the On-Board computer of the
satellite. The digital signal processing algorithms were studied and designed in order to
obtain an optimized hardware implementation. The system was finally implemented and
tested on FPGA Xilinx Virtex 6.
III
The second research concerns the development of a monitoring system for the detection
and signalling of obstacles within the area of the level crossing. The monitoring
system makes use of radar sensors to monitor the observation area. Such sensors have
been chosen over other technologies, due to their lower sensitivity to weather and brightness
variations within the environment in which the system has to operate. The images
from the sensors are processed in order to detect still or moving obstacles and to avoid
false alarms caused by the transit of trains. The digital signal processing algorithms used
were developed in hardware studying the best architecture to achieve the integration of
the whole processing system in a single FPGA device and, at the same time, achieve
the real-time processing constraints required by the application. The system was created
and tested on FPGA Xilinx Virtex 6.
The third research activity is related to security in the automotive field. In this field the
new emerging functionalities, the so-called infotainment applications, bring with them a
number of potential risks related to the security of sensitive data and to manipulations of
the on-board electronic of the vehicle and therefore into potential threats to the safety of
passengers. After a study of the state of the art of the existing protection mechanisms
provided for the Electronic Control Units (ECUs) against this kind of threat, it was developed
a hardware IT which implements an encryption algorithm at a high data rate,
meant to be integrated as a peripheral for a processor for automotive applications. The
need for a hardware accelerator for an encryption algorithm is related to the need to support
more and more higher communication speed, especially in the car-to-car type and
car-to-infrastructure applications. The IP was characterized on a Xilinx Virtex 6 FPGA
technology and on standard-cell technology 65nm.
File