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Tesi etd-04252016-231359


Thesis type
Tesi di dottorato di ricerca
Author
CASSETTARI, RICCARDO
URN
etd-04252016-231359
Title
Embedded digital signal processing for on-board satellite and vehicle systems
Settore scientifico disciplinare
ING-INF/01
Corso di studi
INGEGNERIA
Commissione
tutor Prof. Fanucci, Luca
Parole chiave
  • space
  • Digital signal processing
  • automotive
Data inizio appello
25/05/2016;
Consultabilità
parziale
Data di rilascio
25/05/2019
Riassunto analitico
The research activity reported in this thesis is focused on the study of efficient solutions<br>to meet the challenges in the design of electronic systems for satellites and vehicles,<br>and more particularly on blocks of digital signal processing within these systems. More<br>in detail, this thesis describes three research activities on innovative solutions for some<br>sub-systems related to the fields of space and vehicles.<br>The first research activity is devoted to the realization of a transponder Telemetry,<br>Tracking &amp; Command (TT&amp;C) innovative optimized for small satellites with type Earth<br>Observation missions (EO). The activity was carried out in collaboration with Intecs and<br>Sitael companies. The miniaturization of the satellite is a more and more important factor,<br>as it allows to reduce the mission costs due to the reduction of the satellite’s mass. One<br>of the most innovative aspects of the system is therefore the integration of the scientific<br>data transmission unit with the TT&amp;C sub-system of the satellite in a single FPGA device,<br>which allows to reduce the mass of the electronics board. Another innovative aspect of<br>the system developed is the in-flight re-configurability of the communication parameters in<br>order to optimize the communication link between the Earth and the satellite. This feature<br>is very important for satellites for Earth Observation, which typically have a Low Earth<br>Orbit (LEO). The designed system includes a part of signal processing in the transmission<br>and reception chains and a control part and interface with the On-Board computer of the<br>satellite. The digital signal processing algorithms were studied and designed in order to<br>obtain an optimized hardware implementation. The system was finally implemented and<br>tested on FPGA Xilinx Virtex 6.<br>III<br>The second research concerns the development of a monitoring system for the detection<br>and signalling of obstacles within the area of the level crossing. The monitoring<br>system makes use of radar sensors to monitor the observation area. Such sensors have<br>been chosen over other technologies, due to their lower sensitivity to weather and brightness<br>variations within the environment in which the system has to operate. The images<br>from the sensors are processed in order to detect still or moving obstacles and to avoid<br>false alarms caused by the transit of trains. The digital signal processing algorithms used<br>were developed in hardware studying the best architecture to achieve the integration of<br>the whole processing system in a single FPGA device and, at the same time, achieve<br>the real-time processing constraints required by the application. The system was created<br>and tested on FPGA Xilinx Virtex 6.<br>The third research activity is related to security in the automotive field. In this field the<br>new emerging functionalities, the so-called infotainment applications, bring with them a<br>number of potential risks related to the security of sensitive data and to manipulations of<br>the on-board electronic of the vehicle and therefore into potential threats to the safety of<br>passengers. After a study of the state of the art of the existing protection mechanisms<br>provided for the Electronic Control Units (ECUs) against this kind of threat, it was developed<br>a hardware IT which implements an encryption algorithm at a high data rate,<br>meant to be integrated as a peripheral for a processor for automotive applications. The<br>need for a hardware accelerator for an encryption algorithm is related to the need to support<br>more and more higher communication speed, especially in the car-to-car type and<br>car-to-infrastructure applications. The IP was characterized on a Xilinx Virtex 6 FPGA<br>technology and on standard-cell technology 65nm.
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