• behavioral modeling
• chip
• co-simulation
• high-speed
• ibis
• lpddr
• macromodeling
• memory
• modeling
• mpilog
• phy
• physical layer
• pop
• power integrity
• semiconductors
• signal integrity
• silicon
• sip
• soc

The amount of data being transferred across different components of the most modern computing platforms is continuously growing. High-speed wired communication interfaces have been constantly improved over the last years, increasing transmission data-rate, minimizing pin-count and reducing power consumption; this is particularly true in mobile platforms (cellular phones, smart-phones, tablets, etc.), where specialized communication protocols and processing units are specifically designed for a maximum optimization of power efficiency and prevention of electromagnetic interference (EMI). Communication interfaces can support different speeds and voltage levels, adjusted according to the target application (communication to other chips, cameras, displays, batteries, RF transceivers, etc.).
The high-level of integration in state-of-the-art Printed Circuit Boards (PCB), Packages, Systems-in-a-Package (SiP) and Systems-on-Chip (SoC), combined with the inevitable presence of resistive, inductive and capacitive parasitic components of the interconnection structures, often leads to severe system performance degradation. Signal and Power Integrity simulations are required to study the impact of interconnection non-idealities on communication reliability and quality (electrical levels, signal distortions, power-supply fluctuations, Bit-Error-Rate (BER), etc.). Macromodel-based simulations appear to be the only viable approach to deal with the complexity of such analyses: transmitter and receiver circuits (I/Os), usually described by detailed transistor-level netlists, are substituted with accurate and efficient equivalent representations; simulations run much faster, accuracy is guaranteed and system-level verification coverage can be extended.
However, I/O macromodeling has become a more and more challenging task: the increasing communication speed (up to 10Gbps) and the reduction of signal amplitudes require outstanding model accuracy; furthermore, several detrimental effects can be induced by supply-voltage fluctuations, originated by the combination of power distribution network (PDN) non-idealities and I/O dynamic current consumption.
Nowadays, the standard approach for I/O buffer modeling is offered by the Input/Output Buffer Information Specification (IBIS) [5]. IBIS suggests simplified circuit equivalents of typical buffer structures and provides detailed guidelines for the collection of relevant device features via a ready-to-use extraction procedure (e.g., the static characteristics of the output port current, the equivalent capacitance of the silicon die, ...). This specification has been massively used for generating buffer models and it has been continuously updated with additional features and enhancements, becoming a de-facto standard.
In spite of the widely recognized importance and diffusion of IBIS, some specific features of modern I/O devices cannot be accurately reproduced; mostly, the inaccuracies appear to be related with the power supply currents and the dynamic dependence of I/O and supply voltages on circuit’s behavior. In literature, other approaches are available [7, 17, 18, 19, 20, 21, 22]: they complement IBIS and provide improved model accuracy and reasonable efficiency. However, all these approaches do not offer a conclusive reliable tool that accommodates for both single ended and differential devices, with a robust modeling procedure and a satisfying accuracy for high-performance I/O-buffers in complex simulation scenarios.
This research work suggests general and modular modeling solutions, derived from the simple observation of only device external port responses and able to meet all the behavioral requirements.
Starting from state-of-the-art macromodeling techniques described in [4, 5, 6] and [7], this research work proposes enhanced Mpilog macromodels [24, 31, 32]. Results presented in [24] have been acknowledged with the IEEE Best Student Paper Award at 2015 IEEE Signal and Power Integrity, Berlin, Germany, in May 2015.
The model structure is defined by two-piece representations that combine multivariate static surfaces and linear dynamical state-space relations. The static parts are conveniently modeled with compressed tensor approximations [28, 24], thus facilitating their SPICE equivalent synthesis and able to run in any commercial SPICE tool. The dynamical parts are identified using robust time-domain vector fitting algorithms [2, 30]. Overclocking operation is supported and handled by imitating the behavior of the real switching mechanism of output buffers via a simple and reliable solution. Once implemented, the models offer remarkable accuracy and good efficiency figures.
Furthermore, this research has carried out a thorough critical analysis of all the stateof-the-art I/O-buffer macromodeling methodologies, with special focus on the investigation of performance and limitations of IBIS models. Results have been presented in [33], and findings have been acknowledged by the IBIS standardization committee [34]. This research work proposes also e-IBIS, a set of enhancements to the current IBIS specification that have been proven to significantly extend model accuracy in signal and power integrity co-simulation scenarios (see Chapter. 5).
Chapter 1 illustrates state-of-the-art physical implementation techniques of most modern package, PCB and platforms for mobile consumer electronics; characteristics and performances of high-speed physical layers (PHY) for wired communication interfaces are also briefly discussed. Afterwords, signal and power integrity simulation methodologies and challenges are presented, with focus on the requirements for model-based analyses.
Chapter 2 presents the results of a thorough review of state-of-the-art macromodeling techniques for I/O-buffers; model performances and limitations are demonstrated using real system and devices implementations.
Chapter 3 introduces enhanced Mpilog macromodels, discussing and justifying the improvements applied to each model sub-component.
Chapter 4 presented the set of enhancements that this research work has identified and suggested to improve IBIS standard models.
Chapter 5 provides extensive demonstrations of the resulting accuracy of enhanced models; simulations are based on real complex simulation scenarios for single-ended and differential communication interfaces.
Appendix A provides a detailed description of the iterative SVD approximation used to map multi-variate model sub-components; Appendix B, referring to [2], gives an overview on Frequency-Domain and Time-Domain Vector-Fitting algorithms, used for identification and representation of multi-input multi-output dynamic model sub-components.
This thesis eventually ends drawing conclusions on the research findings and outlining open challenges and trends in I/O-buffer macromodeling and model-based signal and power integrity simulations.