Tesi etd-04232019-182142 |
Link copiato negli appunti
Tipo di tesi
Tesi di dottorato di ricerca
Autore
DEL CESTA, SIMONE
URN
etd-04232019-182142
Titolo
DESIGN OF A VERSATILE, FULLY-INTEGRATED SENSOR INTERFACE IN A 0.18 um CMOS TECHNOLOGY
Settore scientifico disciplinare
ING-INF/01
Corso di studi
INGEGNERIA DELL'INFORMAZIONE
Relatori
tutor Prof. Bruschi, Paolo
Parole chiave
- Analog Frontend
- Sensor Interface
Data inizio appello
10/05/2019
Consultabilità
Non consultabile
Data di rilascio
10/05/2089
Riassunto
In the last decades the number of sensors involved in everyday life has been quickly
increased. The growing demand of more accurate sensors and more complex sensors
networks, shown both by consumer and industrial markets, is currently driving
the development of innovative solutions to maximise the data collected from the environment.
In particular, sensors are devices that convert a physical quantity, such as
temperature, humidity or pressure, in an electrical one, enabling the measurement of
environmental parameters. Every one requires a dedicated read-out front-end that, depending
on the sensor nature, has to properly stimulate it and sense its output signal
without affecting it. However, in modern applications, such as the Internet of Things
ones, the reduced available silicon area and the use of battery supplies strongly limit
the number of front-ends embedded in a single device as well the number and variety
of sensors that could be measured by a single device. To overcome this issue, in
the last years researchers made lots of effort in designing general-purpose sensor interfaces
capable of properly stimulate and sense different kind of sensors. However, most
of the proposed in the literature interfaces lack of some functionalities. For example,
some devices are capable of performing only DC measurements, or they are not suitable
for four-contact set-ups. On the contrary, others solutions, such as the AD5933 [1]
of Analog Devices, are capable of executing DC and AC measurements but the operating
frequencies range is smaller than required in many applications. In addition,
many of them are not compliant with modern micro-controller families and with single
cell battery supplies because of a too high minimum required supply voltage. To cope
with all these specifications, since 2012 the Sensichips s.r.l., in partnership with the
Department of Information Engineering of the University of Pisa, is developing a novel
general-purpose sensor interface, the Sensiplus.
The Sensiplus interface is a compact standalone System on a Chip (1.5 mm x 1.5 mm
only) which properly operates from 1.5 V up to 3.3 V of supply voltage with a quiescent
current consumption of only 50 A. It is suitable for a wide number of measurements,
including the AC voltammetry and the Electrical Impedance Spectroscopy, resulting
capable of interfacing a large variety of sensors. In particular, the Sensiplus embeds
up to 15 integrated sensors, including temperature, light and functionalisable ones, and it
could be connected up to 7 different external sensors.
The research activity presented in this thesis started during the development of the
Sensiplus fourth release and consists in the design of three main blocks of the interface:
a new stimulus generator, an innovative Ripple Reduction Loop to be embedded within
the Instrumentation Amplifier, and an improved version of the digital core. These IPs
were integrated in the fourth, fifth and sixth device release in order to validate their
performances by means of electrical measurements.
increased. The growing demand of more accurate sensors and more complex sensors
networks, shown both by consumer and industrial markets, is currently driving
the development of innovative solutions to maximise the data collected from the environment.
In particular, sensors are devices that convert a physical quantity, such as
temperature, humidity or pressure, in an electrical one, enabling the measurement of
environmental parameters. Every one requires a dedicated read-out front-end that, depending
on the sensor nature, has to properly stimulate it and sense its output signal
without affecting it. However, in modern applications, such as the Internet of Things
ones, the reduced available silicon area and the use of battery supplies strongly limit
the number of front-ends embedded in a single device as well the number and variety
of sensors that could be measured by a single device. To overcome this issue, in
the last years researchers made lots of effort in designing general-purpose sensor interfaces
capable of properly stimulate and sense different kind of sensors. However, most
of the proposed in the literature interfaces lack of some functionalities. For example,
some devices are capable of performing only DC measurements, or they are not suitable
for four-contact set-ups. On the contrary, others solutions, such as the AD5933 [1]
of Analog Devices, are capable of executing DC and AC measurements but the operating
frequencies range is smaller than required in many applications. In addition,
many of them are not compliant with modern micro-controller families and with single
cell battery supplies because of a too high minimum required supply voltage. To cope
with all these specifications, since 2012 the Sensichips s.r.l., in partnership with the
Department of Information Engineering of the University of Pisa, is developing a novel
general-purpose sensor interface, the Sensiplus.
The Sensiplus interface is a compact standalone System on a Chip (1.5 mm x 1.5 mm
only) which properly operates from 1.5 V up to 3.3 V of supply voltage with a quiescent
current consumption of only 50 A. It is suitable for a wide number of measurements,
including the AC voltammetry and the Electrical Impedance Spectroscopy, resulting
capable of interfacing a large variety of sensors. In particular, the Sensiplus embeds
up to 15 integrated sensors, including temperature, light and functionalisable ones, and it
could be connected up to 7 different external sensors.
The research activity presented in this thesis started during the development of the
Sensiplus fourth release and consists in the design of three main blocks of the interface:
a new stimulus generator, an innovative Ripple Reduction Loop to be embedded within
the Instrumentation Amplifier, and an improved version of the digital core. These IPs
were integrated in the fourth, fifth and sixth device release in order to validate their
performances by means of electrical measurements.
File
Nome file | Dimensione |
---|---|
La tesi non è consultabile. |