• fault effects
• fault injection
• FPGA
• Xilinx

In the last years, FPGAs have been heavily used in many different critical applications, such as spatial and military ones, where these devices operate in harsh environments. For this reason, research studies about faults (detection, recovery, modelling etc.) in
FPGA technology are of primary concern.
The main objective of this thesis is the development of an integrated environment for the analysis of fault effects in FPGA routing. The integrated environment has been developed as a Python library, named PyXEL, that integrates Xilinx Software, such as Vivado and ISE tools, and exploits a strong know-how to carry out experiments on routing faults in FPGAs in an automated way. In particular, PyXEL provides an easy way to execute design manipulation, fault injection, bitstreams manipulation, collection and analysis of results.
Furthermore, PyXEL has been used for the analysis of fault effects in the interconnection network of the Xilinx Artix-7 XC7A100T FPGA. Routing faults such as conflicts and opens have been injected in the FPGA using randomly chosen Programmable- Interconnect-Points (PIPs). The experiments conducted show that it is possible to use PyXEL in order to gain insights into the real behaviours of fault effects in FPGA routing.