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Digital archive of theses discussed at the University of Pisa


Thesis etd-04152010-141250

Thesis type
Tesi di dottorato di ricerca
Thesis title
Study and design of Turbo and Low-Density Parity-Check Codes decoder architectures for high-rate flexible communication systems
Academic discipline
Course of study
tutor Prof. Saletti, Roberto
relatore Prof. Fanucci, Luca
  • ASIC
  • Flexibility
  • LDPC codes
  • Multi-Standard
  • Turbo codes
Graduation session start date
Release date
This PhD dissertation proposes the ASIC design of a flexible Multi-Standard channel decoder for next generation mobile devices. Nowadays the demand of multi-standard applications is becoming a must for the worldwide user. In such a scenario, a wide range of contents can be provided by integrating onto the same device the support of different communication protocols, both satellite and terrestrial. Flexibility is then the keyword in the design of modern modems and particular attention must be paid to the implementation of the advanced channel coding techniques which represents the most challenging task in terms of computational complexity, speed and power consumption. Among the channel decoding schemes, Turbo and LDPC codes are the preferred choice due to the remarkable error correction performance. To the best of our knowledge, the proposed ad-hoc architecture is the first attempt to design a flexible Multi-Standard channel decoder using an ASIC technology. This represents a very powerful innovation w.r.t. the state-of-the-art channel decoders which are mainly based on application-specific instruction set processor (ASIPs). Actually, an ASIC implementation allows the support of different decoding schemes through the real-time re-configuration of its own hardware resources thus attaining optimized performance in terms of speed area and power consumption.
The BCJR algorithm was identified as the unified basic decoding algorithm since this represents the common choice of the Turbo codes and at the same time the basic engine of the so-called LDPC Turbo-Decoding Message-Passing. The error correction performance were then evaluated by developing an high level model both in floating
and fixed point domain in order to select the most suitable configuration as a trade-off between performance and implementation complexity. Targeting high throughput application the architecture is parallelized by using two different data schedules. On one hand, several distinct data frames can be decoded in parallel through the so-called multi-MAP decoding. On the other hand one single frame is decoded in a parallel manner with the so-called multi-SISO decoding. The power consumption is optimized at two different levels. At the hardware level the resources not used during a particular decoding process are switched off by means of the clock-gating technique. At the algorithmic level stopping rules are employed so as to halt the decoding process as soon as the estimated received word is considered correct. Although a generalization to all the modern communication standards can be easily attained, a proof-of-concept channel decoding platform fully compliant with the IEEE 802.16e, IEEE 802.11n, 3GPP’s and DVB-SH standards was developed. The architecture was then synthesized on a 45 nm CMOS standard-cell library with an operating frequency
of 150 MHz. As a result an area of 0.90 mm2 and a maximum power consumption of 86.1 mW was attained and favourably compared with other state-of-the-art solutions.