• High-Processing Computing
• Error Logging
• Error Reporting
• FPGA
• European Processor Initiative
• HW-SW Interface
• RISC-V
• Reliability-Availability-Serviceability

This thesis aims to develop a Hardware-Software (HW-SW) interface to log information about hardware errors and report them to system software through ad hoc Error Record Banks. The designed Error Logging and Reporting features aim to improve Reliability, Availability, and Serviceability (RAS) in both 32- and 64-bit RISC-V architectures. An HW-SW interface defines the facilities by which hardware errors are logged into banks of registers, with a predefined distribution of the error information, and then reported to system software. This way system software can take actions to recover from hardware errors.
The designed architecture provides the error logging feature through a standard Error Record interface accessible by a memory-mapped protocol, hence it is equipped with an AXI4-Slave controller. At the same time, the error reporting feature can be configured at run-time by writing on the configuration registers.
The HW-SW Interface has been developed in SystemVerilog and verified in the QuestaSim simulator. Then, it was synthesised and implemented within a test System-on-Chip (SoC), featuring the RISC-V CV32E40P core, on the Xilinx ZCU104 evaluation board. The design was also synthesized with two Standard-Cell libraries, 45nm and 7nm, to evaluate the actual area occupation and power consumption.
Overall, the HW-SW Interface has been designed to be flexible and configurable, at implementation time, allowing non-mandatory features to be removed to reduce hardware overhead.