• 65nm
• ASIC
• automotive
• characterization
• controller
• design
• design flow
• Ethernet
• verification
• Verilog

In last years, electronics in automotive showed an important growth and it is still
increasing: nowadays, about one hundred of different electronic systems are contained
within the vehicle. Entertainment and multimedia systems are being added more
and more to traditional electronic systems such as powertrain and safety control: due
to the increasing number of electronic control units inside the vehicle, the volume
and complexity of data that has to be communicated needs a network architecture
with appropriate transfer bandwidth. Some automotive manufacturers are beginning
to replace old and specialized network protocols such as CAN, LIN, ByteFlight
and MOST with more common Ethernet protocol, to decrease complexity of the
network and have appropriate bandwidth. The work presented in this thesis was
carried on at the Department of Information Engineering of University of Pisa, to
develop and design, in collaboration with Renesas Europe, a next generation of
Ethernet controller for automotive applications. The focus of the activity is on data
link layer of the ISO/OSI protocol stack, so on the Ethernet MAC implementation.
The module shall support the 10Mbps, 100Mbps and 1Gbps Ethernet and three
different interfaces: GMII, MII and RMII. The controller is made up of three different
main blocks: this thesis presents the block in charge of interfacing the module to
the physical layer, managing protocol and frequency conversion. According to the
followed design flow, after the understanding of the standard, the micro-architecture
of the block has been defined and described in Verilog. Then the verification phase
has been carried out, in which the functionality of each single sub-block and top
level have been validated. Lastly, the block has been characterized on 65nm CMOS
technology, obtaining meaningful results about area occupation.