• Network-on-Chip
• NoC
• plesiocrono
• sistemi mesocroni
• sistemi plesiocroni
• mesocrono
• wire problem

Digital systems have been continuously improving their performance since the first transistors were put together, according to the Moore law (International Semiconductor Roadmap). However, at present, scalability and flexibility are limited by the difficulty to guarantee correct synchronization obtaining high operating frequencies. A trade-off between complexity and operating frequency exists; in fact, while the complexity increases the operating frequency decreases and vice versa. This is mainly due to the difficulty to keep a tolerable skew between the clock signals at the different synchronous units. Such an issue is known as clock skew problem. In addition, in order to obtain high operating frequencies, regeneration buffers are needed and higher power consumption has to be paid. With the scaling of the integration technology, the clock skew problem is more and more important, and the interconnection delays increase. This drawback, known as wire-delay problem, also limits the performance of the on-chip communication systems and of all the architectures with extensive data-paths.
In the last years, the need to interconnect many functional blocks on a single silicon chip obtaining suitable performance, have implied that architectures based on a shared-bus approach have been replaced by more complex systems based on highly hierarchical structures (AMBA bus, STBus, etc.). However, these solutions are not able to provide the scalability and flexibility degrees required by the future systems with hundred of IP-cores. Recently, an architecture based on a packet-switched approach has been proposed as a solution to the above problem. Such systems are known as Network on Chips (NoCs). Even if NoC architectures offer a good scalable solution, the wire-delay still poses some problems in clock generation and distribution in such complex systems. To overcome the clock skew problem, recently mesochronous communication systems have been proposed. This would enable mitigation of the wire-delay problem simplifying the clock distribution at the back-end phase. This solution does not allow building SoCs with multiple clock domains, but provides an effective solution to fix the clock skew problem. However, existing mesochronous solutions suffer from few problems: high latency, high complexity, clock failure and incompatibility with current design flows. To overcome these limitations, in this dissertation we propose a new mesochronous link architecture, named SKew Insensitive Link (SKIL).
Chapter 1 describes technology scaling trends and gives an overview of how scaling affects digital systems performance. Chapter 2 describes NoC – related concepts and terminology and gives an understanding of the new of thinking that NoCs introduce in digital systems design. Some details about STNoC are also given; it is the AST Microelectronics Grenoble approach to NoCs. Chapter 3 describes various synchronization strategies together with their limitations; attention will be focused on synchronization techniques well suited for NoC systems. Chapter 4 is a summary of solutions existent in literature related to synchronization in NoC – like environments. Chapter 5 presents a link model named SKew Insensitive Link (SKIL); this architecture is patent pending on behalf of AST Microelectronics Grenoble. It proves to be as efficient as other solutions but simpler in implementation. Chapter 6 describes some advanced architectural aspects of SKIL. Chapter 7 reports some results about synthesis and simulations of the SKIL module.