• wire delay
• clock skew
• FIFO synchronizer
• mesochronous

This dissertation presents a technique called SKew Insensitive Link (SKIL) which permits mesochronous communications between two synchronous modules. SKIL is a solution fully supported by ASIC (Application Specific Integrated circuit) semi-custom design flow, with great benefits in terms of time-to-market and costs. SKIL belongs to the class of FIFO (First In First Out) synchronizers, it mitigates the problem of long global wires delay and it resolves clock skew issues, easing the ASIC back-end phase.
Its natural application field is between routers in a Network-On-Chip communication infrastructure, or in general in any System-On-Chip where long wires connect synchronous IPs (Intellectual Property) with skewed clocks.
This dissertation begins with an introduction about networks-on-chip and the wire delay problem in modern VLSI (Very Large Scale Integration) designs. Next is an analysis of the state of the art about existing mesochronous synchronizers. Then SKIL micro-architecture is described and mathematically analyzed to prove the correctness of its operation. Accurate simulations are then carried out to prove the previous analysis.
SKIL was developed in collaboration with STMicroelectronics Advanced System Technology Labs in Grenoble (France) who provides also the CMOS 65 nm standard-cells technology, used to characterize the SKIL.
The simulations and the theoretical analysis show SKIL works properly with arbitrary clock skew and wire delay, provided interconnection links are error-free and do not introduce distortions.