• FPGA
• PUF
• RISC-V
• secure boot

Cybersecurity is an increasingly important aspect of the modern world since most of the communication among electronic devices requires security services like confidentiality, authenticity, and integrity of data. These services can be ensured through a combination of symmetric-key and asymmetric-key cryptography. Eliminating the problem of key management. Most of these approaches are based on Physical Unclonable Functions (PUFs). This thesis focuses on the design, verification, and characterization of a PUF for FPGA technology and its integration into a secure RISC-V-based system on chip to enable an innovative HW/SW secure boot that exploits the proposed PUF. The first part of the thesis concerns the state-of-the-art analysis of PUF devices, their quality metrics, and their role in hardware security and applications. Once the best PUF architectures have been investigated, a Ring Oscillator (RO) PUF has been designed in HDL language and the main merit factors have been intensively tested and evaluated. The second part of the thesis focuses on implementing a secure RISC-V-based system on an FPGA board, where the proposed PUF represents the main building block for the secure boot. The proposed secure system can be used for different purposes: secure boot and secure boot update, generation of keys through the PUF, and execution of cryptographic algorithms in a physically isolated and secure environment.