Tipo di tesi
Tesi di laurea magistrale
Titolo
Design, simulation and layout of a low offset, low noise instrumentation amplifier for a Hall magnetic sensor
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Parole chiave
- hall sensor
- instrumentation amplifier
- nested chopper
- spinning current
Data inizio appello
07/05/2014
Consultabilità
Non consultabile
Data di rilascio
07/05/2084
Riassunto (Italiano)
This thesis deals with the design of a Hall plate magnetic field readout system, and it encompasses the design of both the sensing element and the subsequent preamplifier.
The actual sensor is a Hall plate realized in a standard CMOS digital process, exploiting its N-Well diffusion. A number of solutions have been implemented in order to improve the sensor's performances: temporal averaging (i.e. spinning current), spatial averaging, flicker noise reduction and parasitic field compensation. Moreover, a Verilog A model has been developed and tested, and has been used in circuit simulations.
The preamplifier is a current feedback instrumentation amplifier; it employs input transconductors in order to achieve a high CMRR and PSRR, and a class AB push-pull output stage, which is able to supply high output currents. Moreover, the amplifier is part of a nested-chopper architecture, which is merged with the spinning current technique, in order to reduce as much as possible the residual offset and flicker noise. Thus, the readout system is expected to reach a DC offset variance lower than 5 uT, and an approximately constant noise floor as low as 400 nT/sqrt(Hz) from 100 mHz to 1 kHz.
