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Archivio digitale delle tesi discusse presso l’Università di Pisa

Tesi etd-04032008-115622


Tipo di tesi
Tesi di dottorato di ricerca
Autore
VITUCCI, FABIO
Indirizzo email
fabio.vitucci@iet.unipi.it
URN
etd-04032008-115622
Titolo
Network Processors and Next Generation Networks: Design, Applications, and Perspectives
Settore scientifico disciplinare
ING-INF/03
Corso di studi
INGEGNERIA DELL'INFORMAZIONE
Relatori
Relatore Prof. Russo, Franco
Relatore Prof. Giordano, Stefano
Parole chiave
  • deep packet inspection
  • misure
  • multiprocessore
  • network processor
  • traffic classification
Data inizio appello
09/06/2008
Consultabilità
Completa
Riassunto
Network Processors (NPs) are hardware platforms born as appealing solutions for packet processing devices in networking applications. Nowadays, a plethora of solutions exists, with no agreement on a common architecture. Each vendor has proposed its specific solution and no official standard still exists.
The common features of all proposals are a hierarchy of processors, with a general purpose processor and several units specialized for packet processing, a series of memory devices with different sizes and latencies, a low-level programmability. The target is a platform for networking applications with low time to market and high time in market, thanks to a high flexibility and a programmability simpler than that of ASICs, for example.
After about ten years since the "birth" of network processors, this research activity wants to make an analytical balance of their development and usage. Many authoritative opinions suggest that NPs have been "outdated" by multicore or manycore systems, which provide general purpose environments and some specialized cores. The main reasons of these negative opinions are the hard programmability of NPs, which often requires the knowledge of private microcode, or the excessive architectural limits, such as reduced memories and minimal instruction store.
Our research shows that Network Processors can be appealing for different applications in networking area, and many interesting solutions can be obtained, which present very high performance, outscoring current solutions. However, the issues of hard programming and remarkable limits exist, and they could be alleviated only by providing almost a comprehensive programming environment and a proper design in terms of processing and memory resources. More e cient solutions can be surely provided, but the experience of network processors has produced an important legacy in developing packet processing engines.
In this work, we have realized many devices for networking purposes based on NP platform, in order to understand the complexity of programming, the flexibility of design, the complexity of tasks that can be implemented, the maximum depth of packet processing, the performance of such devices, the real usefulness of NPs in network devices. All these features have been accurately analyzed and will be illustrated in this thesis. Many remarkable results have been obtained, which confirm the Network Processors as appealing solutions for network devices. Moreover, the research on NPs have lead us to analyze and solve more general issues, related for instance to multiprocessor systems or to processors with no big available memory. In particular, the latter issue lead us to design many interesting data structures for set representation and membership query, which are based on randomized techniques and allow for big memory savings.
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