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Tesi etd-03302021-201855


Tipo di tesi
Tesi di laurea magistrale
Autore
D'AGOSTINO, LORENZO
URN
etd-03302021-201855
Titolo
Design and FPGA implementation of an AWGN generator as channel emulator in satellite communication: the CCSDS 131.2-B case study
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
EMBEDDED COMPUTING SYSTEMS
Relatori
relatore Prof. Fanucci, Luca
relatore Ing. Falaschi, Francesco
relatore Ing. Bertolucci, Matteo
Parole chiave
  • ESA
  • testbed
  • CCSDS 131.2-B
  • on-board implementation
  • matlab modelling
  • vhdl description
  • satellite communication
  • channel emulator
  • awgn generator
Data inizio appello
30/04/2021
Consultabilità
Non consultabile
Data di rilascio
30/04/2091
Riassunto
Nowadays, the increasing amount of data produced by scientific missions has required the development of technologies and protocols for a higher quality telemetry downlink.
An increasing number of space agencies have had the need to define a new standard for this type of communication, whose main characteristics are reliability and high speed.
Therefore, the Consultative Committee for Space Data Systems has defined the CCSDS 131.2-B as a flexible and advanced coding and modulation scheme for high rate telemetry applications.
In order to test and evaluate the standard, while avoiding the huge costs of space missions, a testbed was provided for the protocol.
One of the impairments which compose the channel emulator is the Additive White Gaussian Noise generator.
An analysis of the characteristics of both the protocol and commercial noise generators was used to define the technical requirements of the module.
For the hardware implementation, instead, an in-depth study of the state of the art has been made in order to choose a specific algorithm.
The next step was the creation, for analysis and validation, of the various MATLAB models of the architecture, gradually getting closer and closer to the hardware implementation.
The hardware description of the module, in VHDL, was then simulated in parallel with the MATLAB one in order to verify its correctness.
Finally, the on-board implementation has been realized to verify the results and their compliance with the development requirements.
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