• digital design
• digital design verification
• VHDL
• verifica
• SpaceWire
• UVM

SpaceWire is a communication standard coordinated by the European Space Agency and used for high-speed link and networks aboard spacecrafts. It eases the interconnection of sensors, processing units, telemetry and memories. The main purpose of this standard is to help reduce system integration costs, promote compatibility between data handling equipment and subsystems in order to encourage reuse of data handling equipment across several different missions. Networks can be built using point-to-point data links and routing switches. This work analyses the SpaceWire Router IP from IngeniArs S.r.l. and implements new features described in the latest revision of this standard. It also validates those new features by means of the latest UVM Standard based verification tools that is the state-of-the-art in Digital Design Verification. After a preliminary study, a system design is proposed and discussed thoroughly, with particular emphasis on its standard compliance and marketability.
A UVM-based Verification Environment and a Test Plan were developed to validate the complete Router IP design. Focus of this was the modelization of the router behaviour in all of its features so it can be used to emulate the router itself and to be sold to verify other standard compliant routers. After design verification, a synthesis process on a target device such as Microchip RTG4 is done to verify if the new design is synthesizable.