Tesi etd-03102016-133251 |
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Tipo di tesi
Tesi di laurea magistrale
Autore
CIARPI, GABRIELE
URN
etd-03102016-133251
Titolo
DESIGN AND VERIFICATION OF AN INDUCTORLESS DCDC CONVERTER FOR 48V AUTOMOTIVE APPLICATIONS in 350 nm CMOS TECHNOLOGY: FOCUSING ON A WIDE INPUT VOLTAGE STEP UP/ STEP DOWN STAGE
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Relatori
relatore Prof. Fanucci, Luca
relatore Prof. Saponara, Sergio
relatore Prof. Saponara, Sergio
Parole chiave
- Automotive Applications
- Converter
- DCDC
- Inductorless
Data inizio appello
06/05/2016
Consultabilità
Non consultabile
Data di rilascio
06/05/2086
Riassunto
This thesis is part of the European Project ATHENIS3D. The aim of this thesis is to propose a Switched Capacitor DC-DC
converter to interface the new 48V battery standard for automotive applications. This work lays the basis to extend the application range of switched capacitor DCDC converters also at high voltage automotive world. In particular, it attempts to achieve a fully integrated converter solution for System in Package technology.
The converter has been designed in a HV350nm CMOS Technology, highlighting the advantages and disadvantages of the proposed solution.
The developed system is a isolated converter which produces a regulated outputs (5V and 1.65V) form a 8V to 60V input.
All stages of design have been using "Cadence Virtuoso", starting from a theoretical analysis of the proposed converter, via a transistor-level analysis to arrive at the complete layout of the chip.
converter to interface the new 48V battery standard for automotive applications. This work lays the basis to extend the application range of switched capacitor DCDC converters also at high voltage automotive world. In particular, it attempts to achieve a fully integrated converter solution for System in Package technology.
The converter has been designed in a HV350nm CMOS Technology, highlighting the advantages and disadvantages of the proposed solution.
The developed system is a isolated converter which produces a regulated outputs (5V and 1.65V) form a 8V to 60V input.
All stages of design have been using "Cadence Virtuoso", starting from a theoretical analysis of the proposed converter, via a transistor-level analysis to arrive at the complete layout of the chip.
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