• cmos
• pll
• vco
• high-frequency
• radiation
• rhbd
• communications
• 5G
• IoT

The mobile phone system initially used is the Global System for Mobile Communications (GSM) communication standard later evolved into GPRS (2.5G), EDGE (2.75G), UMTS (3G), HSPA (3.5G) UMTS, LTE (4G) and finally into the new 5G standard. The first two generations supported voice and then text, with 3G defining the transition to broadband access, supporting data rates measured in hundreds of kilobits-per-second. 5G is the 5th generation of mobile networks, and it has been designed to meet the very large growth in data and connectivity of today’s modern society with billions of connected devices, and tomorrow’s innovations. 5G will initially operate with existing 4G networks before evolving to fully stand-alone networks in subsequent releases and coverage expansions. The industry is at 4G (supporting data rates typically measured in the few megabits-per-second) and transitioning to 5G, with the promise of a tenfold increase in data rates. The most important innovations lie in the increased speed of connection and in the highest number of users manageable by a single base station, but the most important is a significant reduction in the latency time. These factors allow the systems to be more real-time and to manage a large data rate devices connected simultaneously.

Since the beginning of the semiconductor electronic industry, the study of circuit reliability has been a hot topic not only for academic purposes but also for industry. The reliability of circuits depends on various factors, and some of them can be controlled such as the fabrication process or the circuit design, but many others are dependent on external factors. The low-cost and readily available CMOS technology is the most integrated technology for high-speed radio frequency transceivers in communications, and it became very popular in the semiconductor industry. The increasing use of electronic systems in harsh environments results in a new challenge to increase electronic reliability and ensure correct behaviour under extreme conditions, such as temperature, radiation, and electromagnetic interference. Especially for the new 5G technology electronic systems must have great reliability for the applications in which they will be used because not always electronic systems work in a safe environment in which the environment itself does not perturb the electronics. For example in space or high energy physic communication applications, the presence of ionizing particles perturb the electronic systems.

After a brief introduction, this thesis presents the design of two different architectures to implement a voltage-controlled oscillator (VCO) for different applications. In particular, it presented the full custom design of an LC-VCO in a commercial 65nm CMOS technology able to operate in high-radiation environments and compliant with the SpaceFibre protocol. Also, total ionizing dose (TID) effects were experimentally investigated with a 10-keV X-ray exposure up to 1 Grad SiO2 level, and from its measurements, it shows an amplitude reduction of 3.65% that induces the small frequency increase of 2.39% when the control voltage assumes the value of VDD/2, and the circuit was still fully functional after a dose of 1 Grad.
The small VCO area and its low power consumption make the controlled oscillator attractive for a fully integrated phase-locked loop (PLL) for a critical front-end application-specific integrated circuit (FE ASIC). In addition, the use of a differential architecture for the cross-coupled cell and its layout as a common centroid technique helps mitigate particle strikes, and considering the results of the VCO measurements, the radiation hardening by design (RHBD) techniques adopted to face radiation problems bring the oscillator to work at the radiation levels needed for the upgrade of the large hadron collider (LHC) experiments.

A second solution to reduce the silicon area occupancy is then presented in which the full custom design of a tapered ring oscillator (RO) VCO based on a commercial 65nm CMOS technology is designed and electrical and thermal characterized up to 160°C. The asymmetrical architecture substantially reduces the Barkhausen amplitude condition and silicon area occupancy at the cost of more power consumption with respect to the symmetric architecture. Nevertheless, the output buffer required for the symmetric RO-VCO certainly has a higher power consumption compared to the power consumption of the asymmetric oscillator to drive the same capacitive load.

Finally, this thesis is concluded with a system-level comparison between different possible PLL implementations to reduce the phase noise and consequently reduce the integrated jitter value on the clock produced by the system itself.
The comparison is made in two different phases. The first is a theoretical comparison between the two samplings technique, voltage, and charge sampling, suggesting that with charge sampling is possible to obtain an ideal 3dB improvement with respect to voltage sampling in the signal-to-noise ratio (SNR). On the contrary, from the whole system comparison made with the developed MATLAB model in the second phase, the voltage sampling (VS) PLL reaches a lower value of integrated jitter with respect to a charge sampling (CS) PLL. The (linear) phase-domain models are considerably more efficient, but the (non-linear) voltage-domain models do a much better job of capturing the details of the loop's behaviour. For these reasons the fourth chapter is focused on the description of an accurate and efficient phase domain model to describe the standard CP-PLL, and the two sub-sampling architectures: voltage and charge sampling PLL.