ETD

Archivio digitale delle tesi discusse presso l'Università di Pisa

Tesi etd-02032020-170800


Tipo di tesi
Tesi di laurea magistrale
Autore
ZANABONI, FRANCESCO
URN
etd-02032020-170800
Titolo
DESIGN, IMPLEMENTATION AND CHARACTERIZATION OF A SPACEFIBRE CODEC ON THE EUROPEAN RAD-HARDENED FPGA NG-MEDIUM
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Relatori
relatore Prof. Fanucci, Luca
relatore Dott. Nannipieri, Pietro
Parole chiave
  • spacefibre
  • ng-medium
  • nanoxplore
  • nanoxmap
  • implementation
  • fpga
  • brave
  • spacewire
  • tool
  • vhdl
Data inizio appello
21/02/2020
Consultabilità
Non consultabile
Data di rilascio
21/02/2090
Riassunto
In the last few years, onboard data-handling for space missions data rate requirement has continuously grown, due to the presence of high-resolution instruments such as Synthetic Aperture Radar or multi-spectral imaging systems. For this reason, the European Space Agency worked on a new communication standard named SpaceFibre, standardized in May 2019. SpaceFibre is the next-generation high-speed onboard communication protocol for satellite data handling. It can run up to 100 Gbps fully exploiting its multi-lane capabilities, with Quality of Service and Fault Detection, Isolation and Recovery. IngeniArs developed in collaboration with the VLSI lab of Università di Pisa a SpaceFibre CODEC IP, which is actively maintained. Rad-Hardened FPGAs where it is possible to implement the SpaceFibre CODEC are followed with interest, one example is the adoption of the BRAVE FPGAs. BRAVE is an FPGA family developed by NanoXplore thanks to Centre National d’Ètudes Spatiales and European Space Agency. These NanoXplore FPGAs are Rad-Hardened and fully designed and fabricate in Europe, which makes it a very strategical product because it permits Europe to be technologically independent of other institutions. The Low-End FPGA, NG-MEDIUM, is already on the market and ready to be used. However, the tools are not mature, indeed in a short time, a lot of versions are released showing fixed bugs, then some components could not always work as expected. The objective of this work is to characterize a SpaceFibre CODEC on the European RAD-Hardened FPGA NG-MEDIUM by designing an appropriate verification set-up, and by critically analyzing the outputs of the tools and by comparing results with the state-of-the-art.
A dedicated design flow has been defined in the NanoXplore environment to implement the IP on the FPGA. The results obtained provide the used resources, timing analysis, and power consumption. All these results are obtained varying the number of Virtual Channels from a minimum of one to a maximum of eight and they are comparable with results available in the literature.
File