• automated workflow
• co-design framework
• cycle-accurate simulation
• design productivity
• heterogenous systems
• risc-v
• system-on-chip
• verification

The complexity of heterogenous Systems on Chip has grown rapidly in the last decades and the effort necessary to set up a verification workflow has increased as well. In this thesis project is developed a flexible, script-based framework used to build up design environments based on RISC-V architecture for assisting hardware/software co-design of heterogeneous systems and low-level cycle-true verification. It reduces the effort needed by the designer to obtain functional, post-synthesis and post-layout outcomes using commercial state of art tools. The novelty introduced by this thesis is the exploitation of the GNU Make build tool. Thanks to its dependency check mechanism and the parallelization capability, it makes the framework able to speed up the design space exploration, reducing the time required to setup a development environment by 70-80%. Setting various properties, the designer can choose and customize the applications to compile, the modules to synthesize, the simulations to perform and whether or not analyze the time-based power consumption of the synthesized modules. The RISC-V open source CPU implementation studied in this thesis has been synthesized and implemented on the Xilinx UltraScale+ ZCU106 evaluation board integrating the FPGA development process into the framework. This work shows how the designer effort is reduced for different application use cases and presents how exploiting the framework versatility can increase the design productivity.