• C2H
• FPGA
• HLS
• DSP
• NIOS
• SoPC

In the embedded system applications the combination of data-processing and system
throughput requirements is constantly increasing. Implementing the algorithm purely in software becomes constantly more difficult because of system power, cost and the limited CPU’s processing capacity. Among all the possible options customizing the CPU’s instruction set for
the specific application and using multiple CPU cores are the most common. A very different
approach is the migration of performance-hungry elements of the algorithm into hardware to
generate hardware accelerators. A hardware accelerator is a block of logic that implements on
silicon the same functions performed by the processor but faster and with a silicon area
occupation. This methodology addresses several important issues:
• Integration with software design-flow
• Direct connection of generated hardware accelerators into the processor’s memory map
• Support for pointers and array
• Efficient latency-aware scheduling and pipelining of memory transactions
The Altera NIOS II C-to-Hardware Compiler (C2H) compiler automates the generation of
hardware accelerators from pure ANSI C functions and its interfacing with the Altera NIOS II
processor, a soft-core processor system implemented on Altera FPGA. The generated
accelerator has direct access to memory and other peripherals in the processor’s system.
This methodology solves also one of the biggest problems in the EDA industry concerning the
incompatibility between hardware and software design flows. The issue is fixed by C2H by
enabling development of embedded software and embedded hardware accelerators and
management of hardware software trade-offs.

The report is organized in 8 Chapters.
The Chapter 1 introduces the internship overview with a brief presentation of the company
Thales Communications of Colombes, Paris (where the internship has been carried out).
The Chapter 2 begins with a brief history of the Electronic Design Automation evolution, with
particular attention to high-level synthesis. In this Chapter is also present a brief description of
the main high-level tools and languages developed in the last years from EDA industry.
The Chapter 3 presents the Altera NIOS II Processor system, its architecture and its
connections. The NIOS II Processor is a fundamental concept in the Altera C-to-Hardware tool comprehension. In fact the C2H tool, as showed in the next chapters, generates hardware
accelerators automatically integrated in the NIOS II processor system, in order to improve its
performances. In the Chapter there is also a brief presentation of the main Altera tools used in
the NIOS II design environment.
The forth Chapter is focused on the C2H compiler. The main features of the tool are examined
and the Design Flow is explained in all its steps. Moreover it is present a brief paragraph
introducing how C2H interacts with the other tools.
The Chapter 4 presents the target hardware used. All the components described are included in
the Cyclone III development kit.
In the Chapter 5 is analyzed the case study, the OFDM Demodulator Algorithm with particular
attention to the software main functions candidates to the acceleration.
The Chapter 6 shows the C2H design flow applied to the case study. It is explained the
acceleration process and some optimisation rules.
The Chapter 7 shows the results in terms of time and area performance on the case study
algorithm.
In the 8 Chapter are summarized the main advantages and drawbacks using C2H and it is present
a brief author’s conclusion.