• downlink
• FPGA
• MATLAB
• satellite
• TWTA
• VHDL
• Xilinx

ACM TESTBED is an ESA project undertaken by the company IngeniArs S.r.l. and aimed at implementing a reference testbed to model the data flow of the new Copernicus Earth Observation missions. A central component under development is the Channel Emulator, i.e. an electronic board that implements several of the impairments affecting satellite links. Among these, the nonlinear distortion introduced by the on-board Travelling Wave Tube Amplifier (TWTA) is the focus of this work. This thesis presents indeed the complete flow of design, verification, implementation, and validation of an IP core for FPGA-based emulation of TWTA nonlinear distortion, targeting a Xilinx RFSoC device. Specifically, the designed IP core processes with real-time constraints an IF signal provided at a sampling rate of 4.096 GHz and implements a configurable distortion based on AM/AM and AM/PM conversions.
The work was structured as follows. The subject of power amplifier behavioural modelling was firstly surveyed to select a subset of models suitable for the target application, which were comparatively tested through simulations in MATLAB. The chosen model has been then translated into a hardware architecture designed in VHDL, which relies on a LUT-based parallel processing approach to cope with the strict timing constraints. After being functionally verified through simulations, the IP core was implemented on the target board, tested using a transmitter and receiver, and successfully validated.