• 65 nm
• Charge Pump
• Frequency Divider
• Loop Filter
• Phase Freqeuncy Detector
• PLL
• Rad-Hard
• TMR
• TSMC

The aim of this work is the design and analysis of a completely integrated solution of a Radiation-hardened Phase-Locked Loop for aerospace environments. These environments are critical for the reliability of electronic devices because of the presence of radiation, which not only degrades the system’s performance, but can also lead to wrong operation. Radiation, interacting with matter, cause two main effects in the silicon and in the oxide called Single Event Effect (SEE) and Total Ionizing Dose (TID). TID is mostly important in High Energy Physics experiments (HEP), in which it can reach values of up to 1 Grad, while in aerospace environment it is usually limited to a few hundred of Krad. Therefore, for aerospace applications SEE is of most interest.
A Phase-Locked Loop (PLL) is a negative feedback loop that generates a periodic signal whose phase and frequency are in a fixed relation with the phase and frequency of the input signal, usually called the reference signal. In every complex system there is the necessity of a reliable and precise clock generator. Although crystal oscillators have these characteristics, they can reach frequencies of at most hundreds of Mega Hertz and, therefore, they can’t afford the necessity of high-speed operation needed today. This is where PLLs find some of their applications. PLLs in general are used in a wide range of circuits like, for example, in RF communication systems and as clock synthesizers in microprocessors as well as in Field Programmable Gate Arrays (FPGA).
Since there are no example of Rad-Hard PLLs in 65 nm TSMC that works in the range of 6÷7 GHz in the literature, in this work a complete project flow is developed: starting from the system-level design of the PLL, all the blocks which it is composed of are completely designed at schematic and layout level. These blocks are the Phase-Frequency detector (PFD), the Charge Pump (CP), the Loop Filter and the Frequency Divider (FD). The PLL has to generate output signals with frequencies 6.25 GHz, 3.125 GHz and 1.5625 GHz starting form a reference frequency of 156.25 MHz, which leads to a divider ratio of 40.
From a system level analysis, the Loop Filter’s components and the CP’s current have been derived taking care on area consumption but also considering tradeoffs in terms of noise and lock time performance. The Loop Filter is a second order filter with a resistor of 12 KΩ and two capacitor of 8 pF and 1 pF respectively and the CP’s current has been chosen to be 40 µA. Moreover, the chosen parameters have been verified through a behavioural model, from which 5.37 MHz of bandwidth and 50° of phase margin results. The Loop Filter’s layout has been designed, resulting in an area consumption of only 6000 µm2.
Three CP’s topologies in their simplest form have been compared, the Drain Switching topology, the Source Switching topology and the Gate Switching topology. From this comparison the best one has been chosen, and a more complex architecture has been developed to enhance the performance. The designed architecture has been characterized in terms of noise and radiation tolerance, also looking at the PLL response to a SET on the CP. The PLL is able to recover the locked state after a particle’s hit on the CP in 300 ÷600 ns.
Regarding the PFD, thanks to its digital nature, the best solution to make it rad-tolerant is the Triple Modular Redundancy technique (TMR). Therefore, some solutions to implement it on the PFD have been analysed and the most robust one has been chosen. The PFD has been developed in both CMOS and CML logic and the CMOS solution has been chosen considering power consumption and noise performance characteristics. The layout has been designed implementing rad-hard layout techniques and has been characterized, resulting in a dead-zone free PFD/CP.
Finally, a three- stage Frequency Divider has been designed and the PLL has been characterized through post-layout simulations. From these simulations a lock time of 1.2 µs and a phase noise below -80 dBc/Hz @ 1 MHz results. This translates into a 2.03 ps RMS of absolute jitter and 14.74 fs RMS of period jitter.
A system view of a possible test chip has also been developed in order to test both the whole PLL and every single block alone. Finally, a floor plan is proposed and, from it, it is possible to estimate a total area of 0.09 mm2, also considering the LC-tank VCO.