• driver rad-hard 28nm CMOS CML optical modulator

The target of this master thesis is to present every step and design choice for the implementation of a rad-hard optical modulator driver. In an environment subjected to radiations, various effects need to be considered to design ICs (Integrated Circuits) such as: TID (Total Ionization Dose) and SEE (Single Event Effect). Both the effects are due to the ionizing particles that hit the semiconductor and the electronic devices. This interaction is simulated with a current stimulus in order to understand how the circuit returns after one of these effects.
We were pushed by the requirement of CERN to have a driver for their optical modulator (ring resonator) and the possibility to scale down the same block already done in 65 nm technology. Before analyzing the design of the final architecture, a small introduction about what happens if an ionizing particle hits the semiconductor is presented, so that the reader may be more confident with radiations environment.
After a survey of the literature, in which some architectures were rejected, we chose and analyzed two kinds of them. Both of them are designed in 28 nm CMOS technology by using Cadence Virtuoso. Before describing them, we highlight that the main project is to make a chip in 28 nm CMOS technology where it is possible to insert a SerDes (Serializer Deserializer) and the driver connected in cascade.
The first architecture is based on inverter CMOS. We will recall how an inverter CMOS works, what is its power consumption and its speed performance. This architecture shows a less radiation hardness in contrast to the CML one. Furthermore, the SerDes output is a differential one so the entire system would need a CMOS-CML level converter (as the input of the driver). Another crucial point is that SerDes needs a small output capacitance as the load, that is easier to obtain with a CML architecture than a CMOS one. Despite all of this, CMOS has some advantages: it needs a smaller area and it has a higher and adjustable output swing.
Before analyzing the CML drivers it is summed up how differential systems work and what the main figures of merit are. We will also illustrate the differences in terms of speed and power consumption performance between CMOS and CML, in addition to how inductive peaking technique works in order to increase the bandwidth.
In both cases, as the load, the equivalent electric circuit of the ring resonator was used. It is connected to the driver through wire bonding and pad model with the aim to get a more realistic simulations. The same was done in the input case by connecting the input of the drivers and the waveform generator. In this last case, a correction was implemented to correct the downgrade of the input signal due to wire bonding.
For each architectures pre-layout and SEE simulations were made in order to understand the main differences in terms of radiation hardness and output swing. Concerning pre-layout simulations the best and the worst case was found after changing the technology corner (slow, typical and fast), a ±10% as the voltage supply variation from the nominal one (900 mV) and scanning [-50 °C;125°C] as temperature range.
As previously said, after a comparison between the output stage driver done with CMOS or CML architecture, the second one was chosen. The layout and post-layout simulations were carried out. The last ones show that the target speed is difficult to reach also in a typical case at room temperature. Eye diagrams at different speeds were plotted (22.2 Gbps and 20 Gbps). They show that at the speed of 20 Gbps, in typical technology corner and at room temperature the amplitude of the eye diagram is guaranteed, while at 125°C in slow technology corner the eye diagram starts to be closed.