• 28nm
• aerospace
• cml
• cmos
• custom
• deserializer
• high speed
• radiations
• rf
• serdes
• serializer

This thesis works proposes a design of a full-custom prototype of a high-speed Serializer-Deserializer (SerDes) circuit for Aerospace applications in a 28nm CMOS technology.
For modern technologies even this type of environment needs an analysis on TID (Total Ionizing Dose) and moreover for SEEs (Single Event Effects) and possible mitigation techniques. Both these phenomena may be referred to the interaction between radiations, ions and heavy particles with Integrated Circuits. TID damages manifest only after a long-time exposure and they lead a progressive downgrading of CMOS electrical features. Meanwhile, SEEs are due to a particle strikes which generate a charge collection in substrate, and they manifest as a injected current peak, influencing device’s behaviour.
First of all, to understand how radiation impacts are critical for nanoscale technologies, an accurate analysis of their effects over IC has to be done. They have been categorized considering consequences over devices. This allows to understand why circuital reliability is important and how it may be related to environmental factors. Then some mitigation techniques have been presented at many levels, showing how their realization may influence the project development.
From literature and direct exploration over some possible architectures, immediately came out that a development at transistor level of a differential circuit, using Current Mode Logic (CML) buffers, was necessary to obtain acceptable results in term of data rate (up to 25Gbit/s), reliability and power consumption.
Thus, a brief recall of differential systems and CML properties has been made, sided by the research of best solutions for encountered architectural problems. From this point begun the realization of a D-type CML latch.
To make the SerDes capable to be compatible with other 28nm circuits (like a Driver, a VCO, a PLL…) technology voltage supply of 900mV has been employed. Afterwards, using latches, a positive edge triggered D-type flip-flop has been designed, and from this first architecture derived other synchronous devices that were necessary for SerDes system.
Then thesis works proceeded with a complete SerDes design, considering various possibilities that involved data transmission, device’s layout organization and the possibility of employ different control signals, considering advantages and drawbacks that each solution may introduce.
Finally, the choice ended over a general-purpose circuit, capable of absolving PISO features (Parallel Input Serial Output) for serialization purposes, and to behave as a SIPO (Serial Input Parallel Output), when data have to be deserialized.
The realization of a single programmable circuit capable of both Ser and Des behaviours, when driven with a Time Division Multiplexing logic (TDM logic), seemed to be interesting. This in fact brings an advantage in terms of power consumption and area occupation, in those systems where a bidirectionality is needed.
Moreover, due to the presence of synchronous elements, it has been necessary the realization of two clock-tree structures, capable of reaching all part of the SerDes with an equally distributed delay. This is inevitable due to the dimensions of device.
Then, an analysis of results has been made in terms of maximum data rate and power consumption for different PVT corners (Process-Temperature-Voltage corner). After that, SEE simulations have been done injecting different quantities of charge in various circuit’s critical nodes, to suggest how the device reacts to incident particles’ fluxes, that can be present in an aerospace environment.
Subsequently, attention was posed over layout design realization. First aim was to try to enhance the reliability of the system adopting some of presented mitigation techniques. Secondly, an accurate and hierarchical positioning of blocks was needed, to obtain a well-organized design of the system.
Design phase was followed by a study over obtained post-layout results. Simulations have highlighted a discrete loss in terms of speed-rate that is related to the presence of parasitic.
The architecture operates at a 12.5Gbit/s data-rate, it is capable of reaching more than 15Gbit/s speed-rate when best environmental conditions are considered, while it is better to slow down transmission to nearly 10Gbit/s in some corners.
Last section has been dedicated to conclusions over the system, a possible floor-plan has been presented, considering the presence of a Ring-Resonator Driver in a single IC. SerDes main drawback in order of integrability is that it is a pad-limited system, which implies a waste in terms of area.
The need of investigate obtained results and compare them with already designed prototypes of SerDes at 65nm CMOS, made this architecture interesting to be realized.