• fpga
• riscv

The company SITAEL S.p.A., which operates in the aerospace sector, defined this thesis work to identify a candidate to replace the two microprocessors in use at the moment, respectively: the LEON2-FT and the OPEN MSP430. The first has an old architecture and software support is now discontinued, the second is limited both by a low operating frequency and a 16-bit architecture.
This is why the company decided to move into the world of RISC-V, which has a large community of developers behind it, promises great flexibility thanks to multiple ISA extensions, and allows the company to cut costs thanks to its open source nature.
The aim of the thesis work is to select, study and modify a RISC-V core to suit the company's needs. The first step was to choose the core. After a very detailed selection among those available on the net, the choice fell on the NEORV32 processor. The core, entirely written in VHDL, has a wide range of ISA extensions that make it useful for multiple applications. After various tests to evaluate the functionality of the processor, the focus of the work shifted to the modification of its architecture.
In the first part, a write-through data cache was designed from an instruction cache already present in the device. The entity was added to the system by modifying the data routing in order to obtain correct access to the memory and other peripheral devices. Subsequently, the internal system memories were removed, replacing them with an interface for an external Magnetic RAM (MRAM) memory. The memory under consideration is very robust and typically used in an aerospace environment. It is an 8bit device, access time of 45ns and 2MB capacity. For the communication between the memory interface and the CPU, which operate with different communication protocols, it was necessary to create a wrapper to enable correct communication between the two devices. After Dhrystone Benchmarking and a synthesis on the Microchip RTG4 radiation tolerant FPGA for aerospace use, it could be observed that the selected NEORV32 core has lower performance than LEON2 due to its simplified architecture based on only two pipes. The core remains, however, an excellent choice from the point of view of area occupancy but also flexibility due to the many ISA extensions of interest to SITAEL such as: compressed instructions, custom instructions and floating point operations. Last but not least, the open source licence allows costs to be cut considerably. Ultimately, RISC-V will definitely be adopted by the company, which will continue with the study and development of this environment.