Sistema ETD

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Tesi etd-04122017-100949


Tipo di tesi
Tesi di laurea magistrale
Autore
GRILLOTTI, FILIPPO
Indirizzo email
filippo.grillotti@gmail.com
URN
etd-04122017-100949
Titolo
Design and implementation of a Self-Checking Metamodel automatic tool for the verification of analog blocks modelled in VHDL.
Struttura
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Commissione
relatore Prof. Fanucci, Luca
Parole chiave
  • analog VHDL
  • testbench
Data inizio appello
05/05/2017;
Consultabilità
parziale
Data di rilascio
05/05/2020
Riassunto analitico
The ASICs in the automotive sensing area are greatly increasing in their complexity. Additional safety mechanisms, DSPs with Firmware and complex output protocols need to be implemented. Due to this increasing complexity of the sensors, an analog top level simulation cannot be used to verify certain chip behaviour during the development phase. Therefore a digital top level simulation is used to verify the chip functionality. The analog blocks need to be modelled in VHDL to simulate design.
In order to receive trustable simulation results, it is needed that the VHDL models match as much as possible the analog circuits. In this context, the VHDL model must be checked against analog simulation in an automatic way. Deviations between the outputs of the VHDL model and the analog simulation, outside a certain limit in time or amplitude, must be detected and displayed.
The aim of this thesis is to develop a verification environment useful for designers to quickly check the behaviour of a VHDL-modelled analog block.
Firstly the VHDL core environment is being implemented using a modular approach for adapting the several internal modules to the model under test. This environment imports data from analog simulation and performs the comparison between the signal producing the reports. Then it is embedded in a Self-Checking Metamodel, a bigger simulation structure that generate the input signals and use them as common input for the analog and the relative VHDL block.
Several scripts are implemented in order to automatize the whole process of verification and to make the system flexible for block interchanging and project portability.
The prototype version released accomplishes the quickness and block interchangeability aimed: the VHDL environment quickly fits the differences between models and shows the divergences between analog and digital behaviour. The tool is also applicable to different projects in order to maintain a useful portability. It has been tested on two different projects, by different users. This tool is really efficient in terms of set up speed and a block simulation can be prepared in a couple of step.
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