ETD system

Electronic theses and dissertations repository


Tesi etd-04102019-140625

Thesis type
Tesi di laurea magistrale
A Python-based framework for supporting virtualized hardware acceleration on FPGA-SoC platforms
Corso di studi
relatore Prof. Buttazzo, Giorgio C.
correlatore Dott. Biondi, Alessandro
correlatore Pagani, Marco
Parole chiave
  • FPGA
  • hardware acceleration
  • APSoC
  • FRED
  • PYNQ
  • Zynq
  • dynamic partial reconfiguration
Data inizio appello
secretata d'ufficio
Data di rilascio
Riassunto analitico
Cyber-Physical System (CPS) typically consist of interacting software and hardware components that must accomplish a set of application-specific while relying on computing platforms with limited resources and being subject to timing, performance, and physical constraints. Modern CPS are characterized by a rich set of requirements that demand for high-performance computations to be accomplished, e.g., self-driving car, structural health monitoring or adaptive control based on Neural Network. To match these requirements, new embedded heterogeneous computing platforms have been developed. They integrate multiple processing cores, possibly with asymmetric computing capabilities and different instruction set architectures, with hardware components that allow accelerating intensive computations, e.g., such as general-purpose graphical processing units (GPGPUs) and field programmable gate arrays (FPGAs).
Xilinx, an American technology company supplier of programmable logic devices, offers the Zynq-7000 and Zynq-Ultrascale system-on-chip (SoC) family,which comprise some of the most promising of such heterogeneous platforms. They integrate multiple types of ARM Cortex processors with FPGA fabrics into a single chip. These platforms allow taking advantage of the rich availability of software systems (such as Linux, device drivers, network stacks, libraries, etc.) while allowing for the deployment of energy-efficient, high-performance hardware accelerators developed in programmable logic. The system interfaces of the accelerators can also be optimized through programmable I/O. Unfortunately, a major limitation of FPGA SoCs is that they are difficult to program and require specialized skills that are typically different from those required by general software programming. For this reason, Xilinx is pushing for tools and frameworks that simplify and make more accessible the programming of Zynq platforms.
As a representative example, Python Productivity for Zynq (PYNQ) is an open-source project from Xilinx that allows embedded programmers to exploit the capabilities of the Zynq without having to design programmable logic circuits. The framework raises the level of programming abstraction using the popular Python language for both the processors and the FPGA. The programmable logic circuits are presented as hardware libraries, called overlays, and are programmed through PYNQ APIs in essentially the same way that software libraries are imported and used. The high-performance hardware functions collectedin an overlay become available to the user application once the FPGA is configured with the bitstream related to that overlay.
Most of Zynq devices offer a Dynamic Partial Reconfiguration (DPR) feature, which makes possible to re-program a portion of the FPGA fabric while the remaining logic resources continue to operate without interruption. This technique allows virtualizing the available area to support several hardware modules in time sharing that would not fit all together (i.e., with a static configuration) on the FPGA fabric. Unfortunately, despite the relevance and the possibilities enabled by this feature, PYNQ does not support a fine-grained control of DPR.
Specifically, PYNQ does not support partial bitstream reconfiguration and only offers the possibility to fully reprogram the FPGA.
Recently, the FRED framework has been proposed to enable a time-predictable exploitation of DPR in the development of real-time applications. It comes with a Linux-based support that includes a predictable resource manager for FPGA reconfiguration requests, a kernel module for implementing a shared-memory communication with hardware accelerators, and an efficient driver to handle FPGA reconfigurations. FRED allows ensuring bounded delays when requesting a dynamic-reconfiguration hardware accelerator.

This thesis integrates the FRED framework into PYNQ with the end of allowing developers to take advantage of DPR in a user-friendly, easy-to-program Python environment. Specifically, a new Python API for FRED has been developed and integrated with the PYNQ infrastructure. Furthermore, several technical aspects have been covered to make the PYNQ Linux image compatible with FRED, producing a set of tools that automatize the required customizations. Finally, a casestudy application based on real-time video processing has been realized to test the developed system. The work of this thesis allows removing the burden from programmers to explicitly manage DPR, and allows relying on predictable FPGA area virtualization while taking advantage of the rich programming libraries available in Python. This work also simplifies the use of the FRED framework, hiding most of the complexity required to develop a DPR-based real-time application.
Indeed, the new Python API for FRED enables an effective exploitation of DPR while keeping a high-abstraction programming level.