Thesis etd-11212018-171144 |
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Thesis type
Tesi di laurea magistrale
Author
BIAGINI, LORENZO
URN
etd-11212018-171144
Thesis title
Worst-Case analysis of a DRAM Controller with FR-FCFS policy
Department
INGEGNERIA DELL'INFORMAZIONE
Course of study
COMPUTER ENGINEERING
Supervisors
relatore Prof. Stea, Giovanni
relatore Ing. Virdis, Antonio
relatore Ing. Virdis, Antonio
Keywords
- DMC
- DRAM
- FRFCFS
- WCD
Graduation session start date
11/12/2018
Availability
Withheld
Release date
11/12/2088
Summary
Analysis of an upper bound on the delay experienced by the access requests targeting the main memory. The worst-case delay is also a starting point to build more useful tools that help with the evaluation of memory performance: the main purpose of this work is, in fact, to derive a minimum service curve for a DRAM whose controller applies a FR-FCFS policy in servicing queued requests. Starting from basic propositions and their proofs, the worst-case is evaluated algorithmically: a particular sequence of events is built that leads to the maximum delay.
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