ETD

• CGRA
• coarse graine reconfigurable array
• integrated circuit
• vectorial processing
• VLSI

In recent years, Coarse-Grained Reconfigurable Arrays (CGRA) appear to be some
of the most interesting options in the field of reconfigurable computing, which has
become very popular in a wide scope of applications, ranging from cryptography
to image processing, from system analysis to general consumer electronics. CGRAs
efficiently accelerate several classes of data-intensive algorithms without giving up
architecture versatility, and their use in machine learning applications is becoming
increasingly widespread. The idea of programming the interconnections between
several Functional Units that perform different operations places them between full
software and fully hardware-programmable solutions. In particular, among all the
Machine Learning algorithms, the typical workload of Convolutional Neural Net-
works fits this kind of architecture very well. These algorithms can benefit from
highly parallel architectures, usually implementing Single Instruction Multiple Data
or Very Long Instruction Word processing schemes. In standard processor array
devices, higher parallelism is achieved by replicating the mapping of a particular
operation over the available processing elements. Using a vectorial architecture,
the resources and the power consumption due to the routing logic and data stream
handling of each Processing Element are reduced proportionally to the number of
vector elements. This work investigates the advantages and costs of enabling confi-
gurable vector processing in CGRA architectures. The primary focus of this thesis
is to implement a configurable vector Processing Element capable of operating with
dynamically reconfigurable data width. This has been achieved starting from a stan-
dard CGRA implementation developed by the University of Pisa. The vectorized
CGRA is validated using a UVM verification environment, comparing its throu-
ghput with the standard implementation. Finally, the vectorial solution has been
synthesised on the TSMC 40nm Standard-Cell technology to compare the cell area
and the estimated power consumption with the standard implementation.