ETD system

Electronic theses and dissertations repository


Tesi etd-08282017-192643

Thesis type
Tesi di laurea magistrale
High-resolution time-to-digital converter for SiPM-based ToF-PET detectors
Corso di studi
relatore Dott. Sportelli, Giancarlo
Parole chiave
  • scintillators
  • TDC
  • time-to-digital converter
  • FPGA
  • PET
  • time-of-flight
  • TOF
  • SiPM
Data inizio appello
Riassunto analitico
Following the recent trend of pushing the time resolution of positron emission tomography (PET) systems for time-of-flight (ToF) acquisitions, this thesis develops a model of time-to-digital converters (TDCs) based on tapped delay lines, suitable for generic FPGAs. The model allows to understand the time resolution limit of this kind of architecture, which is essentially given by the sum of the setup time and hold time of the registers in the FPGA, i.e., down to roughly 30 ps in state-of-the-art devices.

An experimental setup has been realized with a custom-designed PET acquisition system able to acquire signals from two small detectors made of two LYSO crystals of 3 mm x 3 mm x 5 mm coupled to two SiPMs. The developed system features a two-channel TDC based on tapped delay lines, obtained using the carry chains of an Altera Arria 10 SoC-FPGA.
This setup has been used to validate the model and to find the main causes of time resolution loss in the TDC.

Early measurements made after an initial calibration provided an intrinsic time resolution of about 100 ps, which is sensibly worse than the best expected case. Results showed also that there are strong fluctuations in the propagation delay of the TDC buffers during long acquisitions, probably caused by small temperature instabilities. An ad-hoc firmware component has been then specifically designed to re-calibrate continuously the TDCs. With this new procedure, the best achieved time resolution for a single TDC channel becomes 38 ps.
With the LYSO-based detectors, the system shows a coincidence time resolution of 116 ps FWHM, which is comparable with the best results found in literature for similar setups. The implemented data acquisition system uses a very small amount of resources in the FPGA and has a negligible dead time (5 ns) even for the most demanding PET applications.