Thesis etd-06192011-191011 |
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Thesis type
Tesi di laurea specialistica
Author
BRESCIANI, RICCARDO
URN
etd-06192011-191011
Thesis title
Static Analysis of Circuits for Security
Department
INGEGNERIA
Course of study
INGEGNERIA ELETTRONICA
Supervisors
relatore Prof. Fanucci, Luca
Keywords
- sicurezza
- verifica formale
- VHDL
Graduation session start date
22/07/2011
Availability
Full
Summary
The purpose of the present work is to define a methodology to analyze a system description given in VHDL code and test its security properties. In particular the analysis is aimed at ensuring that a malicious user cannot make a circuit output the secret data it contains.
File
| Nome file | Dimensione |
|---|---|
| Static_A...urity.pdf | 2.43 Mb |
| Static_A...72011.pdf | 2.95 Mb |
| Static_A...ndout.pdf | 1.77 Mb |
| Static_A...t_2x1.pdf | 1.76 Mb |
| Static_A...t_4x1.pdf | 1.75 Mb |
| Static_A...72011.pdf | 2.51 Mb |
| Static_A...ndout.pdf | 2.13 Mb |
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