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Tesi etd-06192011-191011


Thesis type
Tesi di laurea specialistica
Author
BRESCIANI, RICCARDO
URN
etd-06192011-191011
Title
Static Analysis of Circuits for Security
Struttura
INGEGNERIA
Corso di studi
INGEGNERIA ELETTRONICA
Commissione
relatore Prof. Fanucci, Luca
Parole chiave
  • VHDL
  • sicurezza
  • verifica formale
Data inizio appello
22/07/2011;
Consultabilità
completa
Riassunto analitico
The purpose of the present work is to define a methodology to analyze a system description given in VHDL code and test its security properties. In particular the analysis is aimed at ensuring that a malicious user cannot make a circuit output the secret data it contains.