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Tesi etd-06182019-155446


Thesis type
Tesi di laurea magistrale
Author
BELLI, JACOPO
URN
etd-06182019-155446
Title
Design and Validation of a Hardware Random Number Generator for Security Applications
Struttura
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Supervisors
relatore Prof. Fanucci, Luca
tutor Dott. Baldanzi, Luca
tutor Dott. Crocetti, Luca
Parole chiave
  • generator
  • security
  • crytptography
  • entropy
  • source
  • drbg
  • csprng
  • rng
  • trng
  • fpga
  • asic
  • SP800_90
  • SP800_22
  • number
  • random
Data inizio appello
19/07/2019;
Consultabilità
Secretata d'ufficio
Data di rilascio
19/07/2089
Riassunto analitico
Random numbers are widely employed in cryptography and security applications and represent one of the main aspects to take care of along a chain of security. For instance, random numbers are employed for the creation of keys, which are used to encrypt data. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the encryption key, breaking even the strongest implementation of a cipher.

The work presented herein describes the design and the validation of a digital Random Number Generator (RNG) as hardware accelerator for cryptographically secure applications. After a preliminary study of literature and standards specifying requirements for random number generation, it is illustrated the design flow of a RNG, implemented in SystemVerilog language, from specifications definition phase, up to the synthesis phase.

The overall design has been tested and validated by means of official test suites released by third party organizations, assessing the randomness degree of generated output. The module passed all tests of NIST Statistical Test Suite, thus stating that the sequences of bits generated cannot be distinguished from a true random sequence of numbers.

The RNG synthesized on Intel Stratix IV requires up to 6200 Adaptive Logic Modules and supports a throughput of 720 Mbps, while on Silvaco 45nm standard-cell technology it supports a throughput up to 4 Gbps with a maximum logic complexity of 124 kGE.
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