ETD system

Electronic theses and dissertations repository


Tesi etd-04162018-111041

Thesis type
Tesi di dottorato di ricerca
Advanced VLSI architectures and design methodologies for automotive applications
Settore scientifico disciplinare
Corso di studi
tutor Prof. Fanucci, Luca
Parole chiave
  • 3D Hall sensing
  • automotive
  • security
  • AES
  • HW acceleration
  • Side Channel Attack
Data inizio appello
Data di rilascio
Riassunto analitico
The research reported in this thesis focuses on efficient solutions to address the challenges in the design of electronic systems in the automotive domain.
In particular, this thesis describes three research activities focused on automotive innovative solution ranging from digital processing systems for smart sensor conditioning to the development of security systems for data protection and authentication.

The first research activity addresses the implementation of a digital processing system for a 3D Hall sensors integrated circuit.
The work, in collaboration with ams AG company, was mainly focused on the research and evaluation of the trade-offs for an implementation suitable for the automotive industry.
A simulation model was developed to verify the response to physical stimuli and to evaluate system precision.
A reconfigurable digital solution was designed with a particular attention to reducing the area and optimizing the performance of the system while maintaining a suitable level of precision and flexibility.
The system was designed and synthesized using ams 0.35 um standard-cell CMOS technology.

The second research activity is dedicated to the design of a novel coprocessor for hardware acceleration of AES-based cryptographic functions, to protect parameters for in-car cryptography and to authenticate software
The aim of the project is to realize a configurable hw/sw architecture, suitable to be integrated in a processor based embedded system.
Optimizations to meet the modern security and complexity requirements of the automotive world were studied in detail and the hw architecture and the software interface were jointly designed to be easily adaptable to different interconnect infrastructures.
The prototype was implemented on a Xilinx Zynq-7000 SoC, where the system complexity and the latency performance were verified.

The third research activity focuses on the development of a simulated methodology to evaluate the effectiveness of Side Channel Attack countermeasures for the Advanced Encryption Standard.
The methodology, instead of performing the countermeasure evaluation on the physical implementation, uses the power extracted from gate level implementations by means of power simulations and then elaborated by a statistical model.
Differential and Correlation Power Analysis attacks were simulated and tested on an AES implementation, comparing the results of the model.
Using the methodology, the appropriate SCA countermeasures can be preliminary benchmarked at design time, shortening the evaluation phase and reducing development costs while allowing the designer to explore the wider design space available.