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Tesi etd-04142020-154805


Thesis type
Tesi di laurea magistrale
Author
PACINI, TOMMASO
URN
etd-04142020-154805
Title
Design of a FPGA-based CNN Hardware Accelerator for the ESA CloudScout Project
Struttura
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Supervisors
relatore Prof. Fanucci, Luca
Parole chiave
  • FPGA
  • Hardware Accelerator
  • ESA
  • Earth Observation
  • CloudScout
  • CNN
Data inizio appello
05/05/2020;
Consultabilità
Secretata d'ufficio
Data di rilascio
05/05/2090
Riassunto analitico
CloudScout is a project funded by the European Space Agency and led by the company Cosine Remote Sensing (NL), with the participation of the University of Pisa (IT), Sinergise (SL) and Ubotica Technologies (IR).
The project targets the development of an Artificial Intelligence algorithm based on Convolutional Neural Networks to implement cloud detection on-board the satellite. The mission selected for the in-orbit demonstration is the PhiSat-1 / FSSCAT mission of the European Space Agency to be flown in 2020.
At present, the network is deployed on the Eyes of Things board, a Commercial Off-the-Shelf device featuring the Intel Movidius Myriad-2 Visual Processing Unit not designed for the space radiation environment.
The low radiation tolerance characteristics of the Myriad-2 do not allow its use for long-lasting Medium Earth Orbit and Geosynchronous Equatorial Orbit missions.
To overcome the above rad-hard limit, this thesis addresses the development of the first FPGA-based accelerator for CloudScout.
The designed system successfully combines the high complexity of the network with the limited resource availability of FPGA devices. This result has been achieved by developing a custom architecture that optimizes the use of on-chip and off-chip memories.
A proper scheduling of load, compute and store operations has been conceived to reduce the overhead times introduced by off-chip data transfers.
The processing core is a flexible hardware solution that provides high performance and guarantees high efficiency in computational resources management.
The design has been implemented on the Zynq UltraScale+ XCZU7EV and on the Kyntex Ultrascale XCKU060 FPGAs to extract the main hardware accelerator metrics.
The achieved inference times are respectively 211ms and 303ms while the on-chip powers amount to 3.15W and 3.45W.
When compared to the 350ms and 1.8W of the Myriad 2 VPU implementation, these results indicate that the FPGA-based solutions provide better performance at the cost of an increased power consumption.
The proposed implementations are meant to be a first step toward the use of rad-hard FPGAs, which, contrary to COTS devices, would allow to extend CloudScout application to long-lasting Medium Earth Orbit and Geosynchronous Equatorial Orbit missions.
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