ETD

• Benchmarking
• FPGA
• GPU
• INT8
• ISA Extension
• SIMD
• Space

The initial goal of this thesis was to extend the Instruction Set Architecture (ISA) of GPU@SAT, a soft GPU IP core based on a 32-bit architecture and compliant with the OpenCL 1.2 programming model, to support vector operations. GPU@SAT is often used as a co-processor to accelerate typical Machine Learning tasks, such as convolutional layers. Expanding its computational unit to execute multiple 8-bit operations would significantly increase parallelism, reducing inference time and improving compatibility with ML frameworks such as TensorFlow Lite, which supports 8-bit fixed-point quantization.
Building on this objective, the ISA of the GPU was modified following an initial phase of software testing for the new instructions. After validating their functionality, benchmarking activities were conducted on an FPGA to evaluate performance improvements compared to the baseline scalar architecture.