ETD system

Electronic theses and dissertations repository


Tesi etd-01222016-111504

Thesis type
Tesi di laurea magistrale
Step-down switched-capacitor DC-DC converter for system-on-chip applications
Corso di studi
relatore Prof. Iannaccone, Giuseppe
Parole chiave
  • Step-down
  • switched-capacitor
  • DC-DC
  • converter
Data inizio appello
Data di rilascio
Riassunto analitico
This thesis presents a fully integrated switched capacitor DC/DC converter for

System on Chip applications, designed in 40nm CMOS process. The converter

is designed for a 2.5 ÷ 4.5V input voltage, a 0.5 ÷ 1.5V output voltage and a

500n÷1.5mA output current. A system efficiency grater than linear regulator’s

is achieved for every loading condition.

A review of losses mechanism in basic a charge pump circuit is provided

and a generic equivalent model is introduced. With the simplified model the

charge-pump is represented as an ideal transformer followed by an equivalent

output resistance. In particular, charge vector analysis is reviewed and used

to evaluate the output resistance of different charge pumps circuits and hence

their performances. A specific charge-pump topology is chosen that meets our

technological requirements in terms of switches maximum voltage rating. The

charge-pump’s driving circuits are designed to properly drive the switches using

a 2V externally provided supply voltage. Capacitors layout is chosen to mini-
mize parasitic losses and to achieve the highest capacitive density at the same

time. Later, the performances of the charge pump are investigated and the

degrees of freedom (DoF) - including switch size and operative frequency - are

chosen to improve system efficiency. A double control loop is designed, providing a coarse and a fine regulation: the inner loop adjusts the effective frequency

of the charge-pump’s driving circuit so that output regulation is achieved, while

the coarse feedback loop changes the charge-pump’s configuration to track peak

efficiency depending on the loading conditions. For this purpose, a digital block

is designed for loading condition detection, making possible to chose the best

system configuration with no trial and error approach. Both control loops are

first simulated using Verilog-A blocks and the specifications of each block are

defined to meet the required performances of the converter. In particular, the

bandwidth of the inner regulation-loop’s comparator is designed to meet output

ripple specification and a total biasing current budget is set to achieve higher

than LDO efficiency in sub − 1μW output power. Later, all analog blocks of

the control loop are designed and simulated in Cadence suite, over a variety of

temperatures, process corners and mismatches. Finally, system performances -

such as efficiency, output ripple, system step-response, battery charge/discharge

and reference voltage variations - are evaluated. Our converter is designed to

work over a very wide range of loading conditions, from sub-μW to few mW

of output power, achieving a 70% peak efficiency. Remarkable performances

are achieved under very-light load condition thanks to a particularly optimized

static biasing of the analog blocks.