• RISC-V
• Rocket
• microelectronics
• space processor
• ISA

The state of the art in terms of space on-board computing platform is composed by: the LEON4, a Scalable Processor Architecture (SPARC) 32-bit core developed by Cobham Gaisler mainly for the European market, and the RAD5500, a PowerPC 64-bit core developed by BAE Systems for the American one. Future space missions would impose heavier constraints on low-power and performance requirements in order to fulfill more demanding computational applications. In addition, due to the greater complexity of these applications, the support for a full Operative System (OS), as Linux, is required.

The goal of this thesis is to evaluate, design and implement an open-source available RISC-V core into a radiation-hardened library, the Gaisler Research Library IP (GRLIB). The RISC-V Instruction Set Architecture (ISA) is an open-source architecture developed at Berkley (USA) that leverage the the principles of Reduced Instruction Set Computing (RISC) architectures and it is reasonably scalable to several kind of processor applications. The design would then be evaluated in terms of architectural complexity, power and performance metrics.

A Rocket RISC-V core has been selected as open-source processor implementation and the design has been validated on a Xilinx VC-707 Field Programmable Gate Array (FPGA) platform. Mentor ModelSim has been used as Simulation tool and Xilinx Vivado as the Synthesis one.

Results show that the RISC-V GRLIB design uses 29\% of the FPGA resources with an estimated power consumption of 2.951 W running at 100 MHz. The core achieves a Dhrystone score of 1.17 DMIPS/MHz and a Whetstone score of 0.86 WMPIS/MHz, both comparable to the ones achieved by the state of the art. Finally the portability of the RISC-V GRLIB design allow the implementation of a Rocket RISC-V core in many other FPGA platforms.