Tesi etd-10302020-145544 |
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Tipo di tesi
Tesi di laurea magistrale
Autore
CAVERNI, MARTA
URN
etd-10302020-145544
Titolo
Enhancing motor control example design by simulating motor kit in FPGA
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Relatori
relatore Prof. Saletti, Roberto
tutor Jeppesen, Ben
tutor Jeppesen, Ben
Parole chiave
- FPGA
- motor control
- PMSM
- real time simulation
Data inizio appello
20/11/2020
Consultabilità
Non consultabile
Data di rilascio
20/11/2090
Riassunto
FPGAs can integrate on a single device high speed/high accuracy motor and power control. To demonstrate a motor control design target control device and motor kit are needed. The presented project describes how the use of FPGAs can go further and include not only the control design, but also a real time model of the motor kit used to test it. This will lead to the reduction of costs and supply issues related to the physical motor kit.
Several steps has been followed to create the simulation. First one was software only. A C function replicating the behaviour of a permanent magnet synchronous motor (PMSM) runs real time on the embedded processor. Then the software algorithm was converted to a IP using Simulink libraries. The IP is programmed on the FPGA fabric, but is directly called by software using the Avalon Memory-Mapped interface. The IP is in single floating point precision, this has the advantage to be easier to design, but the drawbacks of long execution time and high resource usage. In order to create an IP able to run fast enough (MHz) the third step consisted in converting the floating point model to fixed point precision. This required a careful numerical design to maintain accuracy, keep the resource usage down and provide a faster execution.
Several steps has been followed to create the simulation. First one was software only. A C function replicating the behaviour of a permanent magnet synchronous motor (PMSM) runs real time on the embedded processor. Then the software algorithm was converted to a IP using Simulink libraries. The IP is programmed on the FPGA fabric, but is directly called by software using the Avalon Memory-Mapped interface. The IP is in single floating point precision, this has the advantage to be easier to design, but the drawbacks of long execution time and high resource usage. In order to create an IP able to run fast enough (MHz) the third step consisted in converting the floating point model to fixed point precision. This required a careful numerical design to maintain accuracy, keep the resource usage down and provide a faster execution.
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