• self test
• safety critical
• memory test
• instruction based test
• Cortex-A
• cache test
• ARM
• software based test

The contribution of this thesis is to design and implement safety-critical mechanisms applicable to the application class processor as ARM Cortex-A.
The problem analyzed is the software-based self-test for Level 2 caches controllers in ARM Cortex-A processors; in particular, the focus is on the address decoder faults and on the test of cache coherence logic. The main difficult related to these problems is that the cache system is hidden to the programmer. After a discussion about solutions provided by both literature and industrial world, the main problems are addressed and, at the end, a solution will be proposed. In the first part of the thesis we design possible solutions addressing theoretical questions, while, in the second part we implement the proposed solutions dealing with practical and developing issues. Meanwhile, we show a study on the theoretical fault coverage based on theorems and mathematical framework.