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Archivio digitale delle tesi discusse presso l’Università di Pisa

Tesi etd-09062015-235709


Tipo di tesi
Tesi di laurea magistrale
Autore
MASCOLO, FILIPPO
URN
etd-09062015-235709
Titolo
Design and implementation of a routing algorithm to maximize test coverage of permanent faults in FPGAs
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA INFORMATICA
Relatori
relatore Prof.ssa Bernardeschi, Cinzia
relatore Prof. Domenici, Andrea
Parole chiave
  • FPGA
  • routing algorithm
  • testing circuit
Data inizio appello
25/09/2015
Consultabilità
Completa
Riassunto
Nowadays electronic devices are used in a huge number of applications, from entertainment market to military equipment, from mobile phones to satellites. Each application has its own requirements and constraints depending on its purpose. One particular kind of applications is the one called mission critical that is characterized by a large amount of money that could be lost if something goes wrong. As an example this is the case of satellites that cannot be repaired or returned for maintenance if some parts stop working. When electronic device, and in particular FPGAs, are used in mission critical applications their reliability requires a special attention, therefore a key aspect of them is the capability to tolerate faults. When FPGAs operate in harsh environment, like in space, both temporary and permanent faults can occur due to radiation. The on-line testing technique involves a testing circuit that is capable to test its own used resources. In this work a design and implementation of a routing algorithm to maximize fault coverage of permanent faults is presented.
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