| Tesi etd-08182014-164101 | 
    Link copiato negli appunti
  
    Tipo di tesi
  
  
    Tesi di laurea magistrale
  
    Autore
  
  
    CARATELLI, ALESSANDRO  
  
    Indirizzo email
  
  
    caratelli.a@gmail.com
  
    URN
  
  
    etd-08182014-164101
  
    Titolo
  
  
    Design of a radiation tolerant control ASIC for high energy physics experiments
  
    Dipartimento
  
  
    INGEGNERIA DELL'INFORMAZIONE
  
    Corso di studi
  
  
    INGEGNERIA ELETTRONICA
  
    Relatori
  
  
    correlatore  Kloukinas, Kostas
relatore Prof. Saletti, Roberto
  
relatore Prof. Saletti, Roberto
    Parole chiave
  
  - ASIC
- CERN
- GBT
- HEP
- high energy physics
- LHC
- monitoring
- rad-hard
- radiation tolerant
- SCA
- SEU
- single event upset
- slow control
- slow control
- VLSI
    Data inizio appello
  
  
    26/09/2014
  
    Consultabilità
  
  
    Completa
  
    Riassunto
  
  This work describes the design of a radiation tolerant, monitoring and control ASIC for applications in high-energy physics experiments, called GBT-SCA.
The future upgrades of the LHC will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, a new architecture, referred as GBT system, was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data.
The GBT-SCA, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and monitoring of detector environmental quantities for the future upgrades of the LHC experiments at CERN.
In order to meet the requirements of different front-end ASICs used in multiple experiments, it provides various fully user-configurable protocol ports able to perform simultaneous transfers. Radiation hardening techniques have been applied to ensure robustness against SEUs and TID radiation effects.
The thesis presents the overall architecture of the ASIC describing in detail the design of the peripheral ports, the dual layer communication architecture, the system on chip interconnectivity and the techniques used to mitigate radiation effects, the simulations results and the implementation of the setup for ion beam tests.
    File
  
  | Nome file | Dimensione | 
|---|---|
| Design_o...ments.pdf | 9.45 Mb | 
| Contatta l’autore | |
 
		