• analog-to-digital converters
• digital calibration
• distortion correction
• flash A/D converter
• low-power design
• mixed-signal design
• offset compensation
• optimization
• pipeline A/D converter
• platform-based design
• power scalable circuits
• reconfigurable converters
• regenerative comparators
• robust hierarchical design
• stochastic differential equations
• system-on-chip
• thermal noise
• ultra-wide-band receiver

The “System-on-Chip” (SoC) paradigm has shown many advantages, ranging from cost and chip size reduction to simplifications at the analog-digital interfaces and to global performance improvement. However, seamless integration of analog and mixed-signal processing in scaled technologies presents
several challenges as well. Reduced supply voltages, increased process variation, and declining intrinsic device gains have to be coupled with the requirements of consumer electronics and emerging wireless systems. If further integration of complete systems onto a single die is to continue, innovative solutions have to be embraced at different levels of abstraction: novel methodologies, architectures and circuits. At the system level, a structured methodology that provides efficient exploration of the broad design space and increased support for design reuse has a big potential to limit design iterations and reduce development and production costs. However, for the SoC approach to be economically feasible, design components should be also produced in very large quantities and possibly be shared among several applications, calling, at the implementation level, for scalable circuits, portable across technology nodes and programmable to a certain extent. Although analog design shows some resilience to sharing, flexibility and design reuse, improving on analog scalability becomes a necessity. The goal of this work is to explore a number of plausible paths that lead to truly scalable mixed-signal design and integration in SoCs. Analog-to-Digital Converters (ADCs) are exploited as a demonstrator, being key building blocks of mixed¬signal systems with the most challenging requirements. The first part of this work deals with scalable mixed-signal design from a system perspective, through the formulation of a mixed-signal design methodology based on Platform-Based Design (PBD), an effective paradigm to manage the complexity of hybrid systems and to boost productivity and design quality. In this thesis the extension of this paradigm to mixed-signal design is addressed, coping with the intrinsic nature of analog components, which makes it generally difficult to raise the abstraction level. As a basic tenet of the methodology, design is regarded as a meet-in-the-middle approach, where a bottom-up characterization phase is followed by a top-down exploration phase that maps system specifications onto a well defined architecture space. In the bottom¬up phase hierarchical abstraction of architecture components, organized into libraries (platforms), is tackled by providing accurate performance models. The top-down phase is based on design optimizations performed at the behavioral level of abstraction. Robustness against modeling errors and increased process variability is achieved through maximization of performance margins both at system and architectural levels. The design of a Pipeline ADC for cellular applications is carried out to demonstrate the effectiveness of the methodology, showing that analog/digital trade-offs can be readily evaluated and optimizations can be performed to set optimal analog/digital boundary and performance partitioning. Implementation issues are then covered in the second part of this work, focusing on circuit design and analysis techniques to provide scalable components for future embedded mixed-signal platforms. Basic principles that should inspire embedded analog design are discussed, which culminate in a novel Flash ADC architecture offering power/speed programmability and reconfigurable thresholds. Design guidelines to cope with thermal noise in regenerative circuits are also provided since this is the ultimate performance limitation for similar ADC architectures at low supply voltages. A 4-bit Flash ADC prototype was realized in standard digital 0.18µm CMOS, achieving state-of-the-art energy efficiency and outperforming comparable designs even in more advanced technologies. The ADC was embedded in an impulse-based ultra-wideband receiver enabling the large bandwidth at very low cost and power required by wireless sensor networks. By effectively coupling the bottom-up and top-down aspects of design, the proposed two-tiered multi-disciplinary approach results in a radical departure from the way mixed-signal design is typically done.