• Simulink
• Verilog-AMS
• Physical Layers
• Mixed Signal design
• MATLAB
• Jitter analysis
• High speed serial interfaces
• Behavioural modelling
• VHDL-AMS

This thesis work is the result of a 9 months activity at the IP&Reuse Division - Physical Layer team - of Intel Mobile Communications GmbH in Munich, Germany; the work has been sponsored by the company itself and by an Erasmus grant in the context of ‘LifeLongLearning Program’, academic year 2011-2012.

It has been developed a high-level simulation environment to support the concept, architectural exploration and system-level performance analysis of High Speed Serial Interfaces’ Physical Layer.
Equivalent representation using Analogue Mixed Signal - Hardware Description Languages (HDLs-AMS) have been also implemented to speed-up full chip transistor-level transient simulations.


In Chapter 1 is presented an overview of the state of the art on methodologies, styles, implementation languages and simulation tools used in the design of mixed-signal systems and in the creation of behavioural models. Practical rules for trading off accuracy and speed are also discussed.

In Chapter 2, a high-level description of a generic Physical Layer structure is introduced and all the basic building blocks are analyzed; for each of them it has been implemented a model: the realization methodology is presented and discussed in detail. The focus is put on the analysis of the Transmitter, the PCB interconnection, the Receiver, the Phased Locked Loops (PLLs) and the Clock and Data Recovery (CDR).

Chapter 3 analyzes the fundamental parameters that determine the performances of a Physical Layer; the construction and the use of the Eye diagram are presented together with the actions to extract timing information and, then, to perform a budget. The various types of jitter and the corresponding causes are discussed. A statistical abstraction is introduced toward the computation of the Bit Error Rate (BER).

In Chapter 4, it is illustrated the theory behind a MATLAB script that analyzes the channel pulse response to extract worst-case scenarios and to study the impact of a simple equalizer stage on the overall PHY’s performances; the design key-parameters of this block are then extracted and used in a VHDL-AMS implementation.