Riassunto analitico
The present thesis results from six months internship inside the R&D Labs of STMicroelectronics Belgium N.V.
STMicroelectronics is a Gold Associate Member of the Bluetooth SIG and is part of the radio Improvement Working Group.
The Bluetooth is a wireless communication system and its basic standard (Basic Rate – Bluetooth 1.0) uses a GFSK digital modulation with a maximum bit rate value of 1Mbps.
In order to exchange a larger amount of data, the latest Bluetooth standard (2.0) follows a completely different approach. Two new digital modulation types are now implemented: the pi/4-DQPSK and the 8DPSK. Both are able to increase the bit rate value up to 2Mbps and 3Mbps, respectively.
The objectives related to the various steps of this thesis are the following:
· Architecture analysis of the new modulations schemes, trying to minimize the chip size.
· Investigation of what could be reused of the existing GFSK architecture for the new Modem part.
· Modification of the existing C-simulator in order to simulate the entire Modem functionality of the new EDR standard.
· Performance evaluation and information reporting in order to direct the final chip implementation.
Firstly, the existing C-simulator used for the GFSK Bluetooth standard has been modified in order to simulate the Baseband Enhanced Data Rate Modulator and Demodulator, taking care to insert all the non-ideal effects.
For the transmission filter implementation, two different architectures have been investigated: Look-up Table and Polyphase Filter network.
Although some parts of the Polyphase filtering architecture work at a twice higher frequency in comparison to the LUT case, on equal switching activity conditions both achieve the identical power consumptions. Moreover, within both these filtering architectures, the ROM block occupies at least the 90% of silicon area. Consequently, an implementation through Polyphase network is preferred, obtaining a gain in terms of ROM size occupation approximately of 45% in comparison with the LUT case.
Finally, the transmission filter implementation through Polyphase network with a filter length of 4T results the best trade-off costs/performance solution.
In this way, Modulator architecture related to pi/4-DQPSK and 8DPSK requires in all fourteen ROMs with a total size of 1.75 Kbytes (14x128bits). Furthermore, using a 1.3um technology, the resulting silicon area is about 0.010 mm2.
For both the new DPSK modulations a single FIR SRRC filter is needed and the simulation results show that also in this case a filter length of 4T (53 taps) can be implemented. Besides, referring to the internal structure of the Demodulator, only 4 multipliers and 2 full-adders are required for the Vector Product block, adding a small ROM of 16 bytes size for the 8DPSK Phase Evaluation block.
During this work, a simple algorithm based on the direct demodulation of the Synchronous Sequence has been implemented and may be used for both pi/4-DQPSK and 8DPSK cases in order to avoid a simple doubling of the chip area.
The proposed 8DPSK demodulator architecture results almost redundant, therefore an investigation on other DPSK phase evaluation algorithms is needed. While, for the new Timing Recovery module, several SIG members suggest to use a Semicoherent demodulation scheme in order to achieve better demodulation performance, taking care to respect a low complexity of the implementation.
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